Datasheet

ADMC401
–53–
REV. B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000 00 000
DM (0x2011)
ADC END OF CONVERSION
PWMSYNC
EIU LOOP TIMER TIMEOUT
PIO4 - PIO11 INTERRUPT
EIU COUNT ERROR INTERRUPT
DM (0x201D)
PICMASK (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000000
DM (0x2012)
15 14 13 12 11 10
9
876543210
DM (0x2013)
0 = DISABLE INTERRUPT (MASK)
1 = ENABLE INTERRUPT
PWM TRIP INTERRUPT
PIO3 INTERRUPT
PIO2 INTERRUPT
PIO1 INTERRUPT
PIO0 INTERRUPT
ETU INTERRUPT
11111111
000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000 00 000
AUXCH0 (R/W)
DM (0x2010)
11111111
T
ON, AUX0
= 2  AUXCH0  t
CK
AUXTM0 (R/W)
AUXTM1 (R/W)
T
AUX1
= 2  AUXCH1  t
CK
T
ON, AUX0
= 2  (AUXTM0+1)  t
CK
T
AUX1
= 2  (AUXTM1+1)  t
CK
IN INDEPENDENT MODE
T
OFFSET
= 2  (AUXTM1+1)  t
CK
IN OFFSET MODE
AUXCH1 (R/W)
00000000
00000000
00000000
00000000
00000
Figure 41. Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—
these bits should always be written as shown.