Datasheet

REV. B
ADMC401
–52–
ETUCTRL (R/W)
DM (0x205E)
ETU0
0 = DO NOT CAPTURE
1 = START CAPTURE
DM (0x205D)
ETUDIVIDE (R/W)
DM (0x2050) – DM (0x2056)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DM (0x205C)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETUCONFIG (R/W)
ETU1 MODE
0 = SINGLE SHOT
1 = FREE-RUNNING
ETU1 INTERRUPT
0 = NEXT EVENT A
1 = EVENT B
ETU1 EVENT B
0 = FALLING EDGE
1 = RISING EDGE
ETU1 EVENT A
0 = FALLING EDGE
1 = RISING EDGE
ETU0 EVENT A
0 = FALLING EDGE
1 = RISING EDGE
ETU0 EVENT B
0 = FALLING EDGE
1 = RISING EDGE
ETU0 INTERRUPT
0 = NEXT EVENT A
1 = EVENT B
ETU1 MODE
0 = SINGLE SHOT
1 = FREE-RUNNING
ETUA0 (R)
ETUB0 (R)
ETUAA0 (R)
ETUA1 (R)
ETUB1 (R)
ETUAA1 (R)
ETUTIME (R)
ETU1
0 = DO NOT CAPTURE
1 = START CAPTURE
ETUSTAT (R)
DM (0x205E)
ETU0
0 = NOT CAPTURED
1 = SEQUENCE CAPTURE
ETU1
0 = NOT CAPTURED
1 = SEQUENCE CAPTURED
0000000000000000
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Figure 40. Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.