Datasheet

REV. B
ADMC401
–48–
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000 00000 0
PWMTM (R/W)
DM (0x2008)
PWMCHA (R/W)
PWMCHB (R/W)
PWMCHC (R/W)
DM (0x200C)
DM (0x200D)
DM (0x200E)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 = DISABLE
0 = ENABLE
CH ENABLE
CL ENABLE
BH ENABLE
BL ENABLE
AH ENABLE
AL ENABLE
AH/AL CROSSOVER
BH/BL CROSSOVER
CH/CL CROSSOVER
DM (0x200F)
PWMSEG (R/W)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0100111
0
PWMSYNCWT (R/W)
DM (0x2060)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
PWMSWT (R/W)
DM (0x2061)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000 00000 0
PWMDT (R/W)
DM (0x2009)
PWMGATE (R/W)
DM (0x200B)
GDCLK
1 = ENABLE
0 = DISABLE
LOW-SIDE CHOPPING
HIGH-SIDE CHOPPING
1 = ENABLE
0 = DISABLE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000000000 0
PWMPD (R/W)
DM (0x200A)
00000
0
0
0
0000
0
0
0000
000000 00
0000000 00 0
0
0000
15 14 13 12 11 10
9
8 76543210
000000000 0
0
0
0000
15 14 13 12 11 10
9
8 76543210
000000000 0
0
0
0000
0
0
Figure 36. Structure of Registers of ADMC401
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.