Datasheet

REV. B
ADMC401
–46–
Address Name Type Bits Reset Value Function
0x2046 PIOINTEN R/W [11 ...4] 0x000 PIO Interrupt Enable
0x2047 PIOFLAG R [11 ...4] PIO Interrupt Flag (PIO4 to PIO11)
0x2048–0x204F Reserved
0x2050 ETUA0 R [15 ...0] Event A Capture–Channel 0
0x2051 ETUB0 R [15 ...0] Event B Capture–Channel 0
0x2052 ETUAA0 R [15 ...0] Event AA Capture–Channel 0
0x2053 ETUA1 R [15 ...0] Event A Capture–Channel 1
0x2054 ETUB1 R [15 ...0] Event B Capture–Channel 1
0x2055 ETUAA1 R [15 ...0] Event AA Capture–Channel 1
0x2056 ETUTIME R [15 ...0] ETU Timer Value
0x2057–0x205B Reserved
0x205C ETUCONFIG R/W [7 . . . 0] 0x00 ETU Configuration Register
0x205D ETUDIVIDE R/W [15 ...0] 0x0000 ETU Clock Divide Register
0x205E ETUSTAT R [1 . . . 0] ETU Status Register
0x205F ETUCTRL R/W [1 . . . 0] 0x0 ETU Control Register
0x2060 PWMSYNCWT R/W [7 . . . 0] 0x27 PWMSYNC Width Control
0x2061 PWMSWT R/W [0] 0x0 PWM Software Trip
0x2062–0x206F Reserved
0x2070 EETN R/W [7 . . . 0] 0x00 EET Pulse Decimator Register
0x2071 EETDIV R/W [15 ...0] 0x0000 EET Clock Divider Register
0x2072 EETDELTAT R [15 ...0] 0x0000 EET Delta Timer Register
0x2073 EETT R [15 ...0] 0x0000 EET Timer Period Register
0x2074 EETSTAT R [0] 0x0 EET Status Register
0x2075–0x23FF Reserved
Table IX. DSP Core Register Map of the ADMC401
Address Name Type Bits Function
0x3FFF SYSCNTL R/W [15 . . . 0] System Control Register
0x3FFE MEMWAIT R/W [15 . . . 0] Memory Wait State Control
0x3FFD TPERIOD R/W [15 . . . 0] Interval Timer Period Register
0x3FFC TCOUNT R/W [15 ...0 Interval Timer Count Register
0x3FFB TSCALE R/W [7 . . . 0] Interval Timer Scale Register
0x3FFA SPORT0_RX_WORDS1 R/W [15 . . . 0] SPORT0 Mutlichannel Word 1 Receive
0x3FF9 SPORT0_RX_WORDS0 R/W [15 . . . 0] SPORT0 Mutlichannel Word 0 Receive
0x3FF8 SPORT0_TX_WORDS1 R/W [15 . . . 0] SPORT0 Mutlichannel Word 1 Transmit
0x3FF7 SPORT0_TX_WORDS0 R/W [15 . . . 0] SPORT0 Mutlichannel Word 0 Transmit
0x3FF6 SPORT0_CTRL_REG R/W [15 . . . 0] SPORT0 Control Register
0x3FF5 SPORT0_SCLKDIV R/W [15 . . . 0] SPORT0 Clock Divide Register
0x3FF4 SPORT0_RFSDIV R/W [15 . . . 0] SPORT0 Receive Frame Sync Divide
0x3FF3 SPORT0_AUTOBUF_CTRL R/W [15 . . . 0] SPORT0 Autobuffer Control Register
0x3FF2 SPORT1_CTRL_REG R/W [15 . . . 0] SPORT1 Control Register
0x3FF1 SPORT1_SCLKDIV R/W [15 . . . 0] SPORT1 Clock Divide Register
0x3FF0 SPORT1_RFSDIV R/W [15 . . . 0] SPORT1 Receive Frame Sync Divide
0x3FEF SPORT1_AUTOBUF_CTRL R/W [15 . . . 0] SPORT1 Autobuffer Control Register