Datasheet

ADM691A/ADM693A/ADM800L/M
–11–
REV. 0
RAM Write Protection
The CE
OUT
line drives the Chip Select inputs of the CMOS
RAM.
CE
OUT
follows CE
IN
as long as V
CC
is above the reset
threshold. If V
CC
falls below the reset threshold, CE
OUT
goes
high, independent of the logic level at
CE
IN
. This prevents the
microprocessor from writing erroneous data into RAM during
power-up, power-down, brownouts and momentary power in-
terruptions. The
LOW LINE output goes low when V
CC
falls
below the reset threshold.
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT (WDI)
with an I/O line. When OSC IN and OSC SEL are uncon-
nected, the microprocessor must toggle the WDI pin once every
1.6 seconds to verify proper software execution. If a hardware or
software failure occurs such that WDI not toggled a 200 ms
RESET pulse will be generated after 1.6 seconds. This typi-
cally restarts the microprocessor’s power-up routine. A new
RESET pulse is issued every 1.6 seconds until WDI is again
strobed.
The WATCHDOG OUTPUT (
WDO) goes low if the watch-
dog timer is not serviced within its timeout period. Once
WDO
goes low it remains low until a transition occurs at WDI. The
watchdog timer feature can be disabled by leaving WDI uncon-
nected. OSC IN and OSC SEL also allow other watchdog tim-
ing options.
RESET also goes low if the Watchdog Timer is enabled and
WDI remains either high or low for longer than the watchdog
timeout period.
The
RESET output has an internal 1.6 mA pullup, and can ei-
ther connect to an open collector
RESET bus or directly drive a
CMOS gate without an external pullup resistor.
3V
BATTERY
0.1µF0.1µF
OSC IN
OSC SEL
GND
PFI
NC
0.1µF
RESET
WDO
LOW LINE
SYSTEM STATUS
INDICATORS
RESET
PFO
WDI
CE
IN
CE
OUT
V
BATT
R2
R1
CMOS
RAM
ADDRESS
DECODE
INPUT POWER
+5V
V
CC
BATT
ON
V
OUT
A0–A15
I/O LINE
NMI
RESET
µ P
ADM691A
ADM693A
ADM800L
ADM800M
Figure 24. Typical Application Circuit