Datasheet

ADM6819/ADM6820
Rev. 0 | Page 4 of 12
TIMING DIAGRAMS
V
CC2
V
CC2
OUT
Q1
GATE
LOGIC
V
CC2
V
FET
SETV
EN
0.618V
0.618V
GND
R1
R2
R3
R4
V
CC1
ADM6819
V
CC1
V
CC1
FET
DRIVER
CHARGE
PUMP
UVLO
05133-014
Figure 2. ADM6819 Solution for Validating Two Supplies Before Sequencing
V
SETV
10% 10%
90%
0.618V
V
CC2
+ 5.5V (typ)
V
GATE
t
OFF
t
DELAY
(ADM6819 = 300ms,
ADM6820 = ADJ)
t
ON
05133-015
Figure 3. ADM6819/ADM6820 Timing Diagram Using SETV for Sequencing
V
EN
V
SETV
10% 10%
90%
0.618V
0.618V
V
CC2
+ 5.5V (typ)
V
GATE
t
OFF
t
DELAY
(300ms)
t
ON
0
5133-016
Figure 4. ADM6819 Timing Diagram Using EN and SETV for Sequencing