Datasheet

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 8 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO 1
RE 2
DE
3
DI 4
V
CC
8
B 7
A
6
GND 5
ADM3483E/
ADM3486E
TOP VIEW
(Not to Scale)
06284-004
V
CC
1
RO
2
DI 3
GND 4
A 8
B
7
Z 6
Y 5
ADM3488E/
ADM3490E
TOP VIEW
(Not to Scale)
06284-005
NC 1
RO 2
RE 3
DE 4
V
CC
14
V
CC
13
A 12
B 11
DI
5
Z
10
GND
6
Y
9
GND 7 NC
NC = NO CONNECT
8
ADM3491E
TOP VIEW
(Not to Scale)
06284-006
Figure 4. ADM3483E/ADM3486E
Pin Configuration
Figure 5. ADM3488E/ADM3490E
Pin Configuration
Figure 6. ADM3491E
Pin Configuration
Table 8. Pin Function Descriptions
ADM3483E/
ADM3486E
Pin No.
ADM3488E/
ADM3490E
Pin No.
ADM3491E
Pin No.
Mnemonic Description
1 2 2 RO
Receiver Output. If A > B by 200 mV, RO is high; if A < B by 200 mV,
RO is low.
2 N/A 3
RE Receiver Output Enable. A low level enables the receiver output. A high
level places it in a high impedance state. If RE is high and DE is low, the
device enters a low power shutdown mode.
3 N/A 4 DE
Driver Output Enable. A high level enables the driver differential A and B
outputs. A low level places it in a high impedance state. If
RE is high and DE
is low, the device enters a low power shutdown mode.
4 3 5 DI
Driver Input. With a half-duplex part when the driver is enabled, a logic low
on DI forces A low and B high; a logic high on DI forces A high and B low.
With a full-duplex part when the driver is enabled, a logic low on DI forces Y
low and Z high; a logic high on DI forces Y high and Z low.
5 4 6, 7 GND Ground.
N/A 5 9 Y Noninverting Driver Output.
6 N/A N/A A Noninverting Receiver Input A and Noninverting Driver Output A.
N/A 8 12 A Noninverting Receiver Input A.
N/A 6 10 Z Inverting Driver Output.
7 N/A N/A B Inverting Receiver Input B and Inverting Driver Output B.
N/A 7 11 B Inverting Receiver Input B.
8 1 13, 14 V
CC
Power Supply, 3.3 V ± 0.3 V. Bypass V
CC
to GND with a 0.1 μF capacitor.
N/A N/A 1, 8 NC No Connect. Not internally connected. Can be connected to GND.