Datasheet

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E
Rev. A | Page 10 of 20
V
OL
V
CC
0V
3V
0.25V
IN
OUT
1.5V 1.5V
t
PSL
t
PLZ
V
OM
D
OUT
C
L
= 50pF
2
GENERATOR
1
50
S1
0V OR 3V
V
CC
R
L
= 110
1
PPR = 250kHz, 50% DUTY CYCLE, t
R
 6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-013
Figure 13. Driver Enable and Disable Times (t
PZL
, t
PSL
, t
PLZ
)
3V
0V
V
CC
0V
IN
OUT
V
OM
V
OM
1.5V1.5V
t
RPHL
t
RPLH
GENERATOR
1
50
C
L
= 15pF
2
R
1.5V
0V
V
OM
=
V
CC
2
OUT
V
ID
1
PPR = 250kHz, 50% DUTY CYCLE, t
R
 6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-014
Figure 14. Receiver Propagation Delays
+3V
0V
V
OH
0V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
+3V
0V
V
CC
V
OL
+3V
0V
V
CC
V
OL
+3V
0V
V
OH
0V
+1.5V
+1.5V
+1.5V
IN
OUT
IN
OUT
IN
OUT
IN
OUT
t
RPZL
t
RPSL
t
RPLZ
t
RPHZ
+0.25V
+0.25V
+1.5V
+1.5V
+1.5V
t
RPZH
t
RPSH
R
GENERATOR
1
50
C
L
2
S3
S1
S2
V
CC
+1.5V
–1.5V
V
ID
1k
1
PPR = 250kHz, 50% DUTY CYCLE, t
R
 6.0ns, Z
O
= 50.
2
C
L
INCLUDES PROBE AND STRAY CAPACITANCE.
06284-015
Figure 15. Receiver Enable and Disable Times