Datasheet

ADM3052 Data Sheet
Rev. A | Page 14 of 20
CIRCUIT DESCRIPTION
CAN TRANSCEIVER OPERATION
A CAN bus has two states: dominant and recessive. A dominant
state is present on the bus when the differential voltage between
CANH and CANL is greater than 0.9 V. A recessive state is present
on the bus when the differential voltage between CANH and
CANL is less than 0.5 V. During a dominant bus state, the CANH
pin is high and the CANL pin is low. During a recessive bus state,
both the CANH and CANL pins are in the high impedance state.
ELECTRICAL ISOLATION
In the ADM3052, electrical isolation is implemented on the logic
side of the interface. Therefore, the part has two main sections:
a digital isolation section and a transceiver section (see Figure 30).
The driver input signal, which is applied to the TxD pin and
referenced to the logic ground (GND
1
), is coupled across an
isolation barrier to appear at the transceiver section referenced
to the isolated ground (V
−
). Similarly, the receiver input and V
+
,
which are referenced to the isolated ground in the transceiver
section, are coupled across the isolation barrier to appear at the
RxD pin and V
+SENSE
referenced to the logic ground, respectively.
iCoupler Technology
The digital signals transmit across the isolation barrier using
iCoupler technology. This technique uses chip scale transformer
windings to couple the digital signals magnetically from one
side of the barrier to the other. Digital inputs are encoded into
waveforms that are capable of exciting the primary transformer
winding. At the secondary winding, the induced waveforms are
decoded into the binary value that was originally transmitted.
Positive and negative logic transitions at the input cause narrow
(~1 ns) pulses to be sent to the decoder via the transformer. The
decoder is bistable and is, therefore, set or reset by the pulses,
indicating input logic transitions. In the absence of logic transitions
at the input for more than ~1 μs, a periodic set of refresh pulses,
indicative of the correct input state, is sent to ensure dc correctness
at the output. If the decoder receives no internal pulses for more
than about 5 μs, the input side is assumed to be unpowered or
nonfunctional, in which case the output is forced to a default
state (see Table 9 and Table 10).
TRUTH TABLES
The truth tables in this section use the abbreviations shown
in Table 8.
Table 8. Truth Table Abbreviations
Letter Description
H High level
L Low level
I Indeterminate
X Don’t care
Z High impedance (off)
NC Disconnected
Table 9. Transmitting
Supply Status Input Outputs
V
DD1
V
+
TxD Bus State CANH CANL V
+SENSE
On On L Dominant H L L
On
On
H
Recessive
Z
Z
L
On
On
Floating
Recessive
Z
Z
L
Off On X Recessive Z Z I
On Off L I I I H
Table 10. Receiving
Supply Status Inputs Outputs
V
DD1
V
+
V
ID
= CANH − CANL Bus State RxD V
+SENSE
On On ≥ 0.9 V Dominant L L
On On ≤ 0.5 V Recessive H L
On On 0.5 V < V
ID
< 0.9 V I I L
On On Inputs open Recessive H L
Off On X X I I
On Off X X H H