Datasheet
ADM2484E
Rev. C | Page 14 of 16
APPLICATIONS INFORMATION
ISOLATED POWER SUPPLY CIRCUIT
The ADM2484E requires isolated power capable of 3.3 V at up
to approximately 75 mA (this current is dependent on the data
rate and termination resistors used) to be supplied between the
V
DD2
and the GND
2
pins. A transformer driver circuit with a
center tapped transformer and LDO can be used to generate the
isolated 5 V supply, as shown in Figure 28. The center tapped
transformer provides electrical isolation of the 5 V power
supply. The primary winding of the transformer is excited with
a pair of square waveforms that are 180° out of phase with each
other. A pair of Schottky diodes and a smoothing capacitor are
used to create a rectified signal from the secondary winding.
The ADP3330 linear voltage regulator provides a regulated
power supply to the bus-side circuitry (V
DD2
) of the ADM2484E.
+
IN OUT
SD
ERR
NR
GND
ADP3330
V
CC
V
CC
V
CC
+
3.3V
10µF
22µF
ADM2484E
V
DD1
V
DD2
GND
1
GND
2
SD103C
SD103C
78253
ISOLATION
BARRIER
TRANSFORMER
DRIVER
06984-026
Figure 28. Isolated Power Supply Circuit
PC BOARD LAYOUT
The ADM2484E isolated RS-485 transceiver requires no external
interface circuitry for the logic interfaces. Power supply bypassing
is required at the input and output supply pins (see Figure 29).
Bypass capacitors are conveniently connected between Pin 1
and Pin 2 for V
DD1
and between Pin 15 and Pin 16 for V
DD2
.
Best practice suggests the following:
• A capacitor value between 0.01 µF and 0.1 µF.
• A total lead length between both ends of the capacitor and
the input power supply pin that does not exceed 20 mm.
• Unless the ground pair on each package side is connected
close to the package, consider bypassing between Pin 1 and
Pin 8 and between Pin 9 and Pin 16.
V
DD1
GND
1
RxD
RE
DE
TxD
NC
GND
1
V
DD2
GND
2
A
B
Z
Y
NC
GND
2
NC = NO CONNECT
ADM2484E
06984-027
Figure 29. Recommended PCB Layout
In applications involving high common-mode transients, ensure
that board coupling across the isolation barrier is minimized.
Furthermore, design the board layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this could cause voltage differentials between pins
exceeding the absolute maximum ratings of the device, thereby
leading to latch-up or permanent damage.