Datasheet

REV. –2–
ADM1485–SPECIFICATIONS
(V
CC
= 5 V ⴞ 5%. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
5.0 V R = ∞, Test Circuit 1
2.0 5.0 V V
CC
= 5 V, R = 50 Ω (RS-422), Test Circuit 1
1.5 5.0 V R = 27 Ω (RS-485), Test Circuit 1
V
OD3
1.5 5.0 V V
TST
= –7 V to +12 V, Test Circuit 2
Δ|V
OD
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Test Circuit 1
Common-Mode Output Voltage V
OC
3 V R = 27 Ω or 50 Ω, Test Circuit 1
Δ|V
OD
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
Output Short-Circuit Current (V
OUT
= High) 35 250 mA –7 V ≤ V
O
≤ +12 V
Output Short-Circuit Current (V
OUT
= Low) 35 250 mA –7 V ≤ V
O
≤ +12 V
CMOS Input Logic Threshold Low, V
INL
0.8 V
CMOS Input Logic Threshold High, V
INH
2.0 V
Logic Input Current (DE, DI) ± 1.0 μA
RECEIVER
Differential Input Threshold Voltage, V
TH
–0.2 +0.2 V –7 V ≤ V
CM
≤ +12 V
Input Voltage Hysteresis, ΔV
TH
70 mV V
CM
= 0 V
Input Resistance 12 kΩ –7 V ≤ V
CM
≤ +12 V
Input Current (A, B) 1 mA V
IN
= +12 V
–0.8 mA V
IN
= –7 V
CMOS Input Logic Threshold Low, V
INL
0.8 V
CMOS Input Logic Threshold High, V
INH
2.0 V
Logic Enable Input Current (RE) ± 1 μA
CMOS Output Voltage Low, V
OL
0.4 V I
OUT
= +4.0 mA
CMOS Output Voltage High, V
OH
4.0 V I
OUT
= –4.0 mA
Short-Circuit Output Current 7 85 mA V
OUT
= GND or V
CC
Three-State Output Leakage Current ± 1.0 μA 0.4 V ≤ V
OUT
≤ 2.4 V
POWER SUPPLY CURRENT
I
CC
(Outputs Enabled) 1.0 2.2 mA Digital Inputs = GND or V
CC
I
CC
(Outputs Disabled) 0.6 1 mA Digital Inputs = GND or V
CC
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output t
PLH
, t
PHL
21015 nsR
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, Test Circuit 3
Driver O/P to O/P t
SKEW
15 nsR
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, Test Circuit 3
Driver Rise/Fall Time t
R
, t
F
815 nsR
LDIFF
= 54 Ω, C
L1
= C
L2
= 100 pF, Test Circuit 3
Driver Enable to Output Valid 10 25 ns R
L
= 110 Ω, C
L
= 50 pF, Test Circuit 4
Driver Disable Timing 10 25 ns R
L
= 110 Ω, C
L
= 50 pF, Test Circuit 4
Matched Enable Switching 0 2 ns R
L
= 110 Ω, C
L
= 50 pF, Test Circuit 4*
|t
AZH
–t
BZL
|, |t
BZH
–t
AZL
|
Matched Disable Switching 0 2 ns R
L
= 110 Ω, C
L
= 50 pF, Test Circuit 4*
|t
AHZ
–t
BLZ
|, |t
BHZ
–t
ALZ
|
RECEIVER
Propagation Delay Input to Output t
PLH
, t
PHL
81530 nsC
L
= 15 pF, Test Circuit 5
Skew |t
PLH
–t
PHL
|5nsC
L
= 15 pF, Test Circuit 5
Receiver Enable t
EN1
520 nsC
L
= 15 pF, R
L
= 1 kΩ, Test Circuit 6
Receiver Disable t
EN2
520 nsC
L
= 15 pF, R
L
= 1 kΩ, Test Circuit 6
Tx Pulse Width Distortion 1 ns
Rx Pulse Width Distortion 1 ns
*Guaranteed by characterization.
Specifications subject to change without notice.
(V
CC
= 5 V ⴞ 5%. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
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