Datasheet

ADM12914 Data Sheet
Rev. D | Page 10 of 16
MONITORING PIN CONNECTIONS
Positive Voltage Monitoring Scheme
When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by V
M
, I
M
is the
nominal current through the resistor divider, V
OV
is the over-
voltage trip point, and V
UV
is the undervoltage trip point.
0.5V
UVx
VHx
V
M
VLx
OVx
ADM12914
R
X
V
NH
V
NL
R
Z
R
Y
08265-004
Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration
Figure 17 illustrates the positive voltage monitoring input con-
nection. Three external resistors, R
X
, R
Y
, and R
Z
, divide the
positive voltage for monitoring,V
M
, into high-side voltage,
V
PH
, and low-side voltage, V
PL
. The high-side voltage is con-
nected to the corresponding VHx pin and the low-side voltage
is connected to the corresponding VLx pin.
To trigger an overvoltage condition, the low-side voltage (in this
case, V
PL
) must exceed the 0.5 V threshold on the VLx pin. The
low-side voltage, V
PL
, is given by the following equation:
V5.0=








++
=
Z
YX
Z
OV
PL
RRR
R
VV
Also,
M
M
Z
YX
I
V
RRR =++
Therefore, R
Z
, which sets the desired trip point for the overvoltage
monitor, is calculated using the following equation:
( )
( )
( )
M
OV
M
Z
IV
V
R
)5.0(
=
(1)
To trigger the undervoltage condition, the high-side voltage,
V
PH
, must exceed the 0.5 V threshold on the VHx pin. The
high-side voltage, V
PH
, is given by the following equation:
V5.0=








++
+
=
Z
YX
Z
Y
UVPH
RRR
RR
VV
Because R
Z
is already known, R
Y
can be expressed as follows:
( )
( )
( )
Z
MUV
M
Y
R
IV
V
R −=
)5.0(
(2)
When R
Y
and R
Z
are known, R
X
is calculated using the following
formula:
( )
( )
Y
Z
M
M
X
RR
I
V
R −−=
(3)
If V
M
, I
M
, V
OV
, or V
UV
change, each step must be recalculated.
Negative Voltage Monitoring Scheme
Figure 18 shows the circuit configuration for negative supply
voltage monitoring. To monitor a negative voltage, a 1 V reference
voltage is required to connect to the end node of the voltage
divider circuit. This reference voltage is generated internally
and is output through the REF pin.
0.5V
OVx
VHx
V
M
VLx
UVx
REF
ADM12914
R
Z
V
PH
V
PL
R
X
R
Y
08265-005
Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration
The equations described previously in the Positive Voltage
Monitoring Scheme section need some minor modifications for
use with negative voltage monitoring. The 1 V reference voltage
is added to the overall voltage drop; it must therefore be sub-
tracted from V
M
, V
UV
, and V
OV
before using each in the previous
equations.
To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between the 1 V reference
voltage and the negative supply voltage into high-side voltage,
V
NH
, and low-side voltage, V
NL
. Similar to the positive voltage
monitoring scheme, the high-side voltage, V
NH
, is connected to
the corresponding VHx pin and the low-side voltage, V
NL
, is
connected to the corresponding VLx pin. Refer to the Voltage
Monitoring Example section for further information.
THRESHOLD ACCURACY
The reset threshold accuracy is fundamental, especially at lower
voltage levels. Consider an FPGA application that requires a 1 V
core voltage input with a tolerance of ±5%, where the supply has
a specified regulation, for example, ±2.6%. As shown in Figure 19,
to ensure the supply is within the FPGA input voltage requirement
range, its voltage level must be monitored for UV and OV condi-
tions. The voltage swing on the supply itself causes the voltage
band available for setting the monitoring threshold to be quite
narrow. In this example, the threshold voltages, including the