Datasheet

Data Sheet ADM1276
Rev. C | Page 7 of 48
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Address Set to 11 2 V Connect to VCAP
Input Current for Address 11 3 10 μA
V
ADR
= 2.0 V to VCAP; must not exceed the maximum allowable
current draw from VCAP
SERIAL BUS DIGITAL INPUTS
(SDA, SCL)
Input High Voltage V
IH
1.1 V
Input Low Voltage V
IL
0.8 V
Output Low Voltage V
OL
0.4 V I
OL
= 4 mA
Input Leakage I
LEAK-PIN
−10 +10 μA
−5 +5 μA Device is not powered
Nominal Bus Voltage V
DD
2.7 5.5 V 3 V to 5 V ± 10%
Capacitance for SDA, SCL
Pins
C
PIN
5 pF
Input Glitch Filter
t
SP
0
50
ns
SERIAL BUS TIMING CHARACTERISTICS
Table 2.
Parameter Description Min Typ Max Unit Test Conditions/Comments
f
SCLK
Clock frequency
400
kHz
t
BUF
Bus free time 1.3 µs Following the stop condition of a read transaction
4.7 µs Following the stop condition of a write transaction
t
HD;STA
Start hold time 0.6 µs
t
SU;STA
Start setup time 0.6 µs
t
SU;STO
Stop setup time 0.6 µs
t
HD;DAT
SDA hold time
300
900
ns
t
SU ;DAT
SDA setup time 100 ns
t
LOW
SCL low time 1.3 µs
t
HIGH
SCL high time 0.6 µs
t
R
1
SCL, SDA rise time 20 300 ns
t
F
SCL, SDA fall time 20 300 ns
1
Note: t
R
= (V
IL(MAX)
− 0.15) to (V
IH3V3
+ 0.15) and t
F
= 0.9 V
DD
to (V
IL(MAX)
− 0.15); where V
IH3V3
= 2.1 V, and V
DD
= 3.3 V.
Timing Diagram
t
LOW
t
BUF
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
HIGH
t
R
t
F
t
SU;STO
P
SSP
V
IH
V
IL
V
IH
V
IL
SC
L
SD
A
09718-002
Figure 2. Serial Bus Timing Diagram