Datasheet

Data Sheet ADM1276
Rev. C | Page 33 of 48
GPO2/
ALERT2
PIN BEHAVIOR
The ADM1276 provides a very flexible alert system, whereby
one or more fault/warning conditions can be indicated to an
external device.
FAULTS AND WARNINGS
A PMBus fault on the ADM1276 is always generated due to an
analog event and causes a change in state in the hot swap output,
turning it off. The three defined fault sources are as follows:
• Undervoltage (UV) event detected on the UV pin.
• Overvoltage (OV) event detected on the OV pin.
• Overcurrent (OC) event that causes a hot swap timeout.
Faults are continuously monitored, and, as long as power is
applied to the device, they cannot be disabled. When a fault
occurs, a corresponding status bit is set in one or more
STATUS_xxx registers.
A value of 1 in a status register bit field always indicates a fault
or warning condition. Fault and warning bits in the status
registers are latched when set to 1. To clear a latched bit to 0—
provided that the fault condition is no longer active—use the
CLEAR_FAULTS command or use the OPERATION command
to turn the hot swap output off and then on again.
A warning is less severe than a fault and never causes a change
in the state of the hot swap controller. The sources of a warning
are defined as follows:
• CML: a communications error occurred on the I
2
C bus.
• HS timer was active (HSTA): the current regulation was
active, but did not necessarily shut the system down.
• IOUT OC warning from the ADC.
• IOUT Warning 2 from the ADC.
• VIN UV warning from the ADC.
• VIN OV warning from the ADC.
• VOUT UV warning from the ADC.
• VOUT OV warning from the ADC.
• PIN OP warning from the VIN × IOUT calculation.
GENERATING AN ALERT
A host device can periodically poll the ADM1276 using the
status commands to determine whether a fault/warning is
active. However, this polling is very inefficient in terms of
software and processor resources. The ADM1276 has a
GPO2/
ALERT2
output pin that can be used to generate
interrupts to a host processor.
By default at power-up, the open-drain GPO2/
ALERT2
output is high impedance, so the pin can be pulled high
through a resistor. The FET health bad warning is active by
default on the GPO2/
ALERT2
pin at power-up.
Any one or more of the faults and warnings listed in the Faults
and Warnings section can be enabled and cause an alert, making
the GPO2/
ALERT2
pin active. By default, the active state of the
GPO2/
ALERT2
pin is low.
For example, to use GPO2/
ALERT2
to monitor the VOUT UV
warning from the ADC, the followings steps must be performed:
1. Set a threshold level with the VOUT_UV_WARN_LIMIT
command.
2. Start the power monitor sampling on VOUT.
If a VOUT sample is taken that is below the configured
VOUT UV value, the GPO2/
ALERT2
pin is taken low, signaling
an interrupt to a processor.
HANDLING/CLEARING AN ALERT
When faults/warnings are configured on the GPO2/
ALERT2
pin,
the pin becomes active to signal an interrupt to the processor.
(The pin is active low, unless inversion is enabled.) The
ALERT2
signal on the GPO2/
ALERT2
pin functions as an SMBAlert.
A processor can respond to the interrupt in one of two basic ways:
• If there is only one device on the bus, the processor can
simply read the status bytes and issue a CLEAR_FAULTS
command to clear all the status bits, which causes the deas-
sertion of the GPO2/
ALERT2
line. If there is a persistent
fault—for example, an undervoltage on the input—the
status bits remain set after the CLEAR_FAULTS command
is executed because the fault has not been removed. However,
the GPO2/
ALERT2
line is not pulled low unless a new fault
or warning becomes active. If the cause of the SMBAlert is
a power monitor generated warning and the power monitor
is running continuously, the next sample generates a new
SMBAlert after the CLEAR_FAULTS command is issued.
• If there are several devices on the bus, the processor can
issue an SMBus alert response address command to find
out which device asserted the SMBAlert line. The processor
can read the status bytes from that device and issue a
CLEAR_FAULTS command.
SMBus ALERT RESPONSE ADDRESS
The SMBus alert response address (ARA) is a special address
that can be used by the bus host to locate any devices that need
to talk to it. A host typically uses a hardware interrupt pin to
monitor the SMBus alert pins of a number of devices. When the
host interrupt occurs, the host issues a message on the bus using
the SMBus receive byte or receive byte with PEC protocol.
The special address used by the host is 0x0C. Any devices that
have an SMBAlert signal return their own 7-bit address as the
seven MSBs of the data byte. The LSB value is not used and can
be either 1 or 0. The host reads the device address from the
received data byte and proceeds to handle the alert condition.