Datasheet

Data Sheet ADM1276
Rev. C | Page 21 of 48
TIMER
The TIMER pin handles several timing functions with an
external capacitor, C
TIMER
. The two comparator thresholds are
V
TIMERL
(0.2 V) and V
TIMERH
(1 V). There are four timing current
sources: a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and
a 100 μA pull-down.
These current and voltage levels, together with the value of
C
TIMER
chosen by the user, determine the initial timing cycle
time, the fault current-limit time, and the hot swap retry duty
cycle. The TIMER pin capacitor value is determined using the
following equation:
C
TIMER
= (t
ON
× 60 μA)/V
TIMERH
where t
ON
is the time that the FET is allowed to spend in regu-
lation at the set current limit.
The choice of FET is based on matching this time with the SOA
requirements of the FET. Foldback can be used to simplify the
selection.
When VCC is connected to the backplane supply, the internal
supply of the ADM1276 must be charged up. In a very short
time, the internal supply is fully charged up and, because the
undervoltage lockout (UVLO) voltage is exceeded at VCC, the
device emerges from reset. During this first short reset period,
the GATE and TIMER pins are both held low.
The ADM1276 then goes through an initial timing cycle. The
TIMER pin is pulled high with 3 μA. When the TIMER pin
reaches the V
TIMERH
threshold (1.0 V), the first portion of the
initial timing cycle is complete. The 100 μA current source then
pulls down the TIMER pin until it reaches V
TIMERL
(0.2 V). The
initial timing cycle duration is related to C
TIMER
by the following
equation:
A100
)(
A3
µ
×−
+
µ
×
=
TIMERTIMERLTIMERHTIMERTIMERH
INITIAL
CVVCV
t
For example, a 100 nF capacitor results in a delay of approxi-
mately 34 ms. If the UV and OV inputs indicate that the supply
is within the defined window of operation when the initial timing
cycle terminates, the device is ready to start a hot swap operation.
When the voltage across the sense resistor reaches the circuit
breaker trip voltage, V
CB
, the 60 µA timer pull-up current is
activated, and the gate begins to regulate the current at the current
limit. This initiates a ramp-up on the TIMER pin. If the sense
voltage falls below this circuit breaker trip voltage before the
TIMER pin reaches V
TIMERH
, the 60 µA pull-up is disabled and
the 2 µA pull-down is enabled.
The circuit breaker trip voltage is not the same as the hot swap
sense voltage current limit. There is a small circuit breaker offset,
V
CBOS
, which means that the timer actually starts a short time
before the current reaches the defined current limit.
However, if the overcurrent condition is continuous and the
sense voltage remains above the circuit breaker trip voltage, the
60 µA pull-up remains active and the FET remains in regulation.
This allows the TIMER pin to reach V
TIMERH
and initiate the
GATE shutdown. On the ADM1276, the
LATCH
pin is pulled
low immediately.
In latch-off mode, the TIMER pin is switched to the 2 µA
pull-down when it reaches the V
TIMERH
threshold. The
LATCH
pin remains low. While the TIMER pin is being pulled down,
the hot swap controller remains off and cannot be turned back on.
When the voltage on the TIMER pin goes below the V
TIMERL
threshold, the hot swap controller can be reenabled by toggling
the UV pin or by using the PMBus OPERATION command to
toggle the on bit from on to off and then on again.
HOT SWAP RETRY DUTY CYCLE
The ADM1276 turns off the FET after an overcurrent fault and
then uses the capacitor on the TIMER pin to provide a delay before
automatically retrying the hot swap operation. To configure the
ADM1276 for autoretry mode, the
LATCH
pin is tied to either
the UV pin or to the ENABLE pin. Note that a pull-up resistor
is required on the
LATCH
pin.
When an overcurrent fault occurs, the capacitor on the TIMER
pin is charged with a 60 μA pull-up current. When the TIMER
pin reaches V
TIMERH
, the GATE pin is pulled down. When the
LATCH
pin is tied to the UV pin or the ENABLE pin for auto-
retry mode, the TIMER pin is pulled down with a 2 μA current
sink. When the TIMER pin reaches V
TIMERL
(0.2 V), it automatically
restarts the hot swap operation.
The duty cycle of this automatic retry cycle is set by the ratio
of 2 µA/60 µA, which approximates to being on about 4% of
the time. The value of the timer capacitor determines the on
time of this cycle, which is calculated as follows:
t
ON
= V
TIMERH
× (C
TIMER
/60 μA)
t
OFF
= (V
TIMERH
− V
TIMERL
) × (C
TIMER
/2 μA)
A 100 nF capacitor on the TIMER pin gives an on time of 1.67 ms
and an off time of 40 ms. The device retries indefinitely in this
manner and can be disabled manually by holding the UV or
ENABLE pin low, or by disconnecting the
LATCH
pin. To pre -
vent thermal stress, an RC network can be used to extend the
retry time to any desired level.
FET GATE DRIVE CLAMPS
The charge pump used on the GATE pin is capable of driving
the pin to V
CC
+ (2 × V
CC
), but it is clamped to less than 14 V
above the SENSE± pins and less than 31 V. These clamps ensure
that the maximum V
GS
rating of the FET is not exceeded.