Datasheet

ADM1177 Data Sheet
Rev. C | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC
1
SENSE
2
ON
3
GND
4
TIMER
5
GATE
10
SS
9
ADR
8
SDA
7
SCL
6
ADM1177
TOP VIEW
(Not to Scale)
06047-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCC Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage
lockout (UVLO) circuit resets the ADM1177 when a low supply voltage is detected.
2 SENSE Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current
limit. The hot swap operation of the ADM1177 controls the external FET gate to maintain the (V
CC
− V
SENSE
)
voltage at or below 100 mV.
3 ON Undervoltage Input Pin. Active high pin. An internal undervoltage comparator has a trip threshold of 1.3 V,
and the output of this comparator is used as an enable for the hot swap operation. With an external resistor
divider from VCC to GND, the ON pin can be used to enable the hot swap operation for a specific voltage on
VCC, providing an undervoltage function.
4 GND Chip Ground Pin.
5 TIMER Timer Pin. An external capacitor, C
TIMER
, sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault delay.
The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection
with an external Zener can be used to force this pin high.
6 SCL I
2
C Clock Pin. Open-drain input requires an external resistive pull-up.
7 SDA I
2
C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.
8 ADR I
2
C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four
different I
2
C addresses.
9 SS Soft Start Pin. This pin controls the reference on the current sense amplifier. A 10 µA current source charges
this pin at startup. A capacitor on this pin then sets the slope of the initial current ramp. This pin can also be
driven to a voltage to alter the reference directly, thereby adjusting the current limit level with a gain of 10.
10 GATE GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the
FET drive controller, which utilizes a charge pump to provide a 12.5 µA pull-up current to charge the FET
GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)
by modulating the GATE pin.