Datasheet

ADM1177 Data Sheet
Rev. C | Page 14 of 24
V
VCC
(1)
INITIAL TIMING
CYCLE
(2) (3)(4) (5) (6)
V
ON
V
TIMER
V
GATE
V
SENSE
V
OUT
06047-004
Figure 32. Startup (ON Asserts as Power Is Applied)
INITIAL TIMING
CYCLE
V
VCC
V
ON
V
TIMER
V
GATE
V
SENSE
V
OUT
(1) (2) (3)(4) (5)(6) (7)
06047-005
Figure 33. Startup (ON Asserts After Power Is Applied)
When the initial timing cycle terminates, the device is ready to
start a hot swap operation (assuming that the ON pin is
asserted). In the example shown in Figure 32, the ON pin is
asserted at the same time that V
CC
is applied; therefore, the hot
swap operation starts immediately after Time Point 4. At this
point, the FET gate is charged up with a 12.5 μA current source.
At Time Point 5, the threshold voltage of the FET is reached,
and the load current begins to flow. The FET is controlled to
keep the sense voltage at 100 mV (this corresponds to a
maximum load current level defined by the value of R
SENSE
).
At Time Point 6, V
GATE
and V
OUT
have reached their full
potential, and the load current has settled to its nominal level.
Figure 33 illustrates the situation where the ON pin is asserted
after V
CC
is applied.
HOT SWAP RETRY CYCLE ON THE ADM1177-1
With the ADM1177-1, the device turns off the FET after an
overcurrent fault and then uses the TIMER pin to time a delay
before automatically retrying to hot swap.
As with all ADM1177 devices, an overcurrent fault is timed by
charging the TIMER capacitor with a 60 μA pull-up current.
When the TIMER pin reaches 1.3 V, the fault current limit time
is reached and the GATE pin is pulled down. On the ADM1177-1,
the TIMER pin is then pulled down with a 2 μA current sink.
When the TIMER pin reaches 0.2 V, it automatically restarts the
hot swap operation.
The cooldown period is related to C
TIMER
by Equation 8.
t
COOL
≈ 550 × C
TIMER
ms/μF (8)
Therefore, the retry duty cycle is as given by Equation 9.
t
FAULT
/(t
COOL
+ t
FAULT
) × 100% = 3.8% (9)
SOFT START (SS PIN)
The SS pin is used to determine the inrush current profile.
A capacitor should be attached to this pin. When the FET is
requested to turn on, the SS pin is held at ground until the
SENSE pin reaches a few millivolts. A current source is then
turned on, which linearly ramps the capacitor up to 1.0 V. The
reference voltage for the GATE linear control amplifier is derived
from the soft start voltage, such that the inrush linear current
limit is defined as I
LIMIT
= V
SS
/(10 × R
SENSE
).
This pin can also be driven to a voltage to alter the reference
directly, thereby adjusting the current limit level with a gain
of 10. See Figure 31 for an illustration of this relationship.