Datasheet

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Hot Swap Controller and

Digital Power Monitor with Convert Pin

Data Sheet

ADM1175

Rev. C

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FEATURES

Allows safe board insertion and removal from

a live backplane

Controls supply voltages from 3.15 V to 16.5 V

Precision current sense amplifier

Precision voltage input

12-bit ADC for current and voltage readback

Charge pumped gate drive for external N-channel FET

Adjustable analog current limit with circuit breaker

±3% accurate hot swap current limit level

Fast response limits peak fault current

Automatic retry or latch-off on current fault

Programmable hot swap timing via TIMER pin

Active high and active low ON/ONB pin options

Convert start pin (CONV)

C fast mode-compliant interface (400 kHz maximum)

10-lead MSOP

APPLICATIONS

Power monitoring/power budgeting

Central office equipment

Telecommunications and data communications equipment

PCs/servers

GENERAL DESCRIPTION

The ADM1175 is an integrated hot swap controller and current

sense amplifier that offers digital current and voltage monitoring

via an on-chip, 12-bit analog-to-digital converter (ADC),

communicated through an I

C® interface.

An internal current sense amplifier measures voltage across

the sense resistor in the power path via the VCC pin and the

SENSE pin.

The ADM1175 limits the current through this resistor by

controlling the gate voltage (via the GATE pin) of an external

N-channel FET in the power path. The voltage across the sense

resistor (and, therefore, the inrush current) is kept below a

preset maximum.

The ADM1175 protects the external FET by limiting the time

that the maximum current runs through it. This current limit

period is set by the value of the capacitor attached to the TIMER

pin. Additionally, the device provides protection from overcurrent

events that may occur once the hot swap event is complete. In

the case of a short-circuit event, the current in the sense resistor

exceeds an overcurrent trip threshold, and the FET is switched

off immediately by pulling down the GATE pin.

FUNCTIONAL BLOCK DIAGRAM

ADM1175-1

SENSE

VCC

CONV

1.3V

MUX

12-BIT

ADC

FET DRIVE

CONTROLLER

GND

CURRENT

SENSE

AMPLIFIER

UV COMPARATOR

SDA

SCL

ADR

GATE

TIMER

05647-001

Figure 1.

SENSE

N-CHANNEL FET

P = VI

CONTROLLER

ADM1175-1

SENSEVCC

SDA

SCL

SDA

SCL

GND

GATE

CONV

ADR

TIMER

3.15V TO 16.5V

05647-002

Figure 2. Applications Diagram

A 12-bit ADC can measure the current seen in the sense resistor,

as well as the supply voltage on the VCC pin. An industry-standard

C interface allows a controller to read current and voltage data

from the ADC. Measurements can be initiated by an I

C command

or via the convert (CONV) pin. The CONV pin is especially

useful for synchronizing reads on multiple ADM1175 devices.

Alternatively, the ADC can run continuously, and the user can

read the latest conversion data whenever it is required. Up to four

unique I

C addresses can be created, depending on how the ADR

pin is connected.

The ADM1175 is packaged in a 10-lead MSOP.

Summary of content (24 pages)

PAGE 1
FEATURES APPLICATIONS Power monitoring/power budgeting Central office equipment Telecommunications and data communications equipment PCs/servers GENERAL DESCRIPTION The ADM1175 is an integrated hot swap controller and current sense amplifier that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital converter (ADC), communicated through an I2C® interface.
PAGE 2
ADM1175 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Initial Timing Cycle ................................................................... 13 Applications ....................................................................................... 1 General Description ......................................................................... 1 Hot Swap Retry Cycle on the ADM1175-1 and the ADM1175-3 .................
PAGE 3
Data Sheet ADM1175 SPECIFICATIONS VCC = 3.15 V to 16.5 V; TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted. Table 1.
PAGE 4
ADM1175 Parameter MONITORING ACCURACY 1 Current Sense Absolute Accuracy 0°C to +70°C 0°C to +85°C −40°C to +85°C VSENSE for ADC Full Scale 2 Voltage Sense Accuracy 0°C to +70°C 0°C to +85°C −40°C to +85°C VCC for ADC Full Scale 3 Low Range (VRANGE = 1) High Range (VRANGE = 0) I2C TIMING Low Level Input Voltage, VIL High Level Input Voltage, VIH Low Level Output Voltage on SDA, VOL Output Fall Time on SDA from VIHMIN to VILMAX Maximum Width of Spikes Suppressed by Input Filtering on SDA and SCL Pins Input
PAGE 5
Data Sheet ADM1175 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 2. Parameter VCC Pin SENSE Pin TIMER Pin ON/ONB Pin CONV Pin GATE Pin SDA Pin, SCL Pin ADR Pin Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 20 V 20 V −0.3 V to +6 V −0.3 V to +20 V −0.3 V to +6 V 30 V −0.3 V to +7 V −0.
PAGE 6
ADM1175 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCC 1 ADM1175 9 CONV ON/ONB 3 TOP VIEW (Not to Scale) 8 ADR 7 SDA 6 SCL GND 4 TIMER 5 05647-003 10 GATE SENSE 2 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VCC 2 SENSE 3 ON/ONB 4 5 GND TIMER 6 7 8 SCL SDA ADR 9 CONV 10 GATE Description Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V.
PAGE 7
Data Sheet ADM1175 2.0 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 0.8 1.0 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 2 4 6 8 10 12 14 16 18 VCC (V) 0 –40 10 10 DRIVE VOLTAGE (V) 40 60 80 8 6 4 5V VCC 8 3.15V VCC 6 4 2 2 4 6 8 10 12 14 16 18 VCC (V) 0 –40 05647-029 0 –2 –2 –4 –4 IGATE (µA) 0 –6 –8 –12 –12 10 12 14 16 VCC (V) 18 –14 –40 05647-027 8 60 80 –8 –10 6 40 –6 –10 4 20 Figure 8. Drive Voltage (VGATE − VCC) vs.
PAGE 8
ADM1175 Data Sheet 2.0 12 1.8 10 TIMER THRESHOLD (V) 1.6 6 4 1.4 HIGH 1.2 1.0 0.8 0.6 0.4 2 LOW 0.2 0 2 4 6 8 10 12 14 16 18 VCC (V) 0 05647-031 0 0 2 4 6 8 10 12 14 16 18 VCC (V) Figure 10. Gate Pull-Down Current vs. Supply Voltage at VGATE = 5 V 05647-038 IGATE (mA) 8 Figure 13. Timer Threshold vs. Supply Voltage 2.0 2 1.8 0 1.6 TIMER THRESHOLD (V) –2 IGATE (µA) –4 –6 –8 –10 HIGH 1.4 1.2 1.0 0.8 0.6 0.
PAGE 9
ADM1175 0 –1 –1 –2 –2 –3 –4 –4 –5 –5 2 4 6 8 10 12 14 16 18 VCC (V) –6 –40 –10 –20 –20 –30 –30 ITIMER (µA) –10 –40 –50 –60 –60 –70 –70 4 6 8 10 12 14 16 18 VCC (V) –80 –40 2.5 2.5 2.0 2.0 ITIMER (µA) 3.0 1.5 1.0 0.5 0.5 6 8 10 12 14 16 18 VCC (V) 0 –40 05647-036 4 –20 0 20 40 60 80 1.5 1.0 2 80 Figure 20. Timer Pull-Up Current (Circuit Breaker Delay) vs. Temperature 3.0 0 60 TEMPERATURE (°C) Figure 17.
PAGE 10
ADM1175 Data Sheet 1000 120 900 HITS PER CODE (1000 READS) 115 110 100 95 90 85 4 6 8 10 12 14 16 18 Figure 22. Circuit Breaker Limit Voltage vs. Supply Voltage 400 300 200 0 2046 2047 2048 2049 2050 CODE Figure 25. ADC Noise with Current Channel, Midcode Input, and 1000 Reads 1000 110 108 900 VOCFAST HITS PER CODE (1000 READS) 106 104 102 VLIM 100 98 VOCTRIM 96 94 800 700 600 500 400 300 200 100 92 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 23.
PAGE 11
ADM1175 4 3 3 2 2 1 1 0 0 –1 –1 –2 –2 –3 –3 –4 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 28. INL for ADC –4 0 500 1000 1500 2000 2500 CODE Figure 29. DNL for ADC Rev.
PAGE 12
ADM1175 Data Sheet OVERVIEW OF THE HOT SWAP FUNCTION When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system.
PAGE 13
Data Sheet ADM1175 GATE AND TIMER FUNCTIONS DURING A HOT SWAP OPERATION CALCULATING CURRENT LIMITS AND FAULT CURRENT LIMIT TIME During hot insertion of a board onto a live supply rail at VCC, the abrupt application of supply voltage charges the external FET drain/gate capacitance, which can cause an unwanted gate voltage spike. An internal circuit holds GATE low before the internal circuitry wakes up. This substantially reduces the FET current surges at insertion.
PAGE 14
ADM1175 Data Sheet When the initial timing cycle terminates, the device is ready to start a hot swap operation (assuming that the ON/ONB pin is asserted). In the example shown in Figure 30, the ON pin is asserted at the same time that VCC is applied; therefore, the hot swap operation starts immediately after Time Point 4. At this point, the FET gate is charged up with a 12.5 μA current source.
PAGE 15
Data Sheet ADM1175 VOLTAGE AND CURRENT READBACK The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle, while the selected device waits for data to be read from it or written to it. If the R/W bit is 0, the master writes to the slave device.
PAGE 16
ADM1175 Data Sheet 9 1 9 1 SCL 1 SDA 0 1 1 0 ADRA ADRB D7 R/W D6 D5 ACKNOWLEDGE BY SLAVE START BY MASTER FRAME 1 SLAVE ADDRESS 1 D4 D2 D3 D0 D1 ACKNOWLEDGE BY SLAVE FRAME 2 COMMAND CODE 1 9 9 SCL (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 ACKNOWLEDGE BY SLAVE FRAME 3 DATA BYTE D3 D2 D1 D0 ACKNOWLEDGE BY STOP BY SLAVE MASTER FRAME N DATA BYTE 05647-006 SDA (CONTINUED) Figure 32.
PAGE 17
Data Sheet ADM1175 WRITE AND READ OPERATIONS Table 6. I2C Abbreviations Abbreviation S P R W A N WRITE COMMAND BYTE In the write command byte operation, the master device sends a command byte to the slave device, as follows: 1. 2. 3. Condition Start Stop Read Write Acknowledge No acknowledge 4. 5. 6. QUICK COMMAND The quick command operation allows the master to check if the slave is present on the bus, as follows: 3. 4. The master device asserts a start condition on SDA.
PAGE 18
ADM1175 Data Sheet 7. 8. In the write extended command byte operation, the master device writes to one of the three extended registers of the slave device, as follows: 1. 2. 3. 4. 5. 6. The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA to end the transaction. 1 The master device asserts a start condition on SDA. The master sends the 7-bit slave address, followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA.
PAGE 19
Data Sheet ADM1175 READ VOLTAGE AND/OR CURRENT DATA BYTES For cases where the master is reading voltage only or current only, only two data bytes are read and Step 7 and Step 8 are not required. 1 2 1 B7 V11 B6 V10 B5 V9 B4 V8 B3 V7 B2 V6 B1 V5 B0 V4 I11 I10 I9 I8 I7 I6 I5 I4 V3 V2 V1 V0 I3 I2 I1 I0 Table 13. Voltage Only Readback Format B7 B6 B5 B4 B3 B2 V11 V10 V9 V8 V7 V6 V3 V2 V1 V0 0 0 B1 V5 0 B0 V4 0 Current Readback The ADM1175 digitizes current only.
PAGE 20
ADM1175 Data Sheet Table 15. Status Byte Operations Bit 0 1 2 Name ADC_OC ADC_ALERT HS_OC 3 HS_ALERT 4 OFF_STATUS 5 OFF_ALERT Function An ADC-based overcurrent comparison is detected on the last three conversions An ADC-based overcurrent trip has occurred, causing the alert. Cleared by writing to Bit 4 of the ALERT_EN register. The hot swap operation is off due to an analog overcurrent event. On parts that latch off, this is the same as the HS_ALERT status bit (if EN_HS_ALERT = 1).
PAGE 21
Data Sheet ADM1175 APPLICATIONS INFORMATION APPLICATIONS WAVEFORMS 1 1 2 2 3 3 4 CH2 1.00V CH4 10.0V M40.0ms CH1 1.5A CH3 20.0V Figure 41. Inrush Current Control into 220 µF Load (Channel 1 = ILOAD, Channel 2 = VTIMER, Channel 3 = VGATE, Channel 4 = VOUT) CH2 1.00V CH4 10.0V M10.0ms 05647-073 CH1 1.5A CH3 20.0V 05647-070 4 Figure 44.
PAGE 22
ADM1175 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 46.
PAGE 23
Data Sheet ADM1175 NOTES Rev.
PAGE 24
ADM1175 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices, Inc., or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05647-0-5/12(C) Rev.