Datasheet

Data Sheet ADM1075
Rev. B | Page 9 of 52
Parameter Min Typ Max Unit Test Conditions/Comments
ADR PIN See Table 6
Address Set to 00 0 0.8 V Connect to VEE
Input Current for Address 00 −40 −22 A V
ADR
= 0 V to 0.8 V
Address Set to 01 135 150 165 kΩ Resistor to VEE
Address Set to 10 −1 +1 A No connect state; maximum leakage current allowed
Address Set to 11 2.1 V Connect to VCAP
Input Current for Address 11 3 10 A V
ADR
= 2.0 V to VCAP; must not exceed the maximum
allowable current draw from VCAP
SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL)
Input High Voltage, V
IH
1.1 V
Input Low Voltage, V
IL
0.8 V
Output Low Voltage, V
OL
0.4 V I
OL
= 4 mA, SDAO only
Input Leakage, I
LEAK-PIN
−10 +10 A
−5 +5 A Device is not powered
Nominal Bus Voltage, V
DD
2.7 5.5 V 3 V to 5 V ±10%
Capacitive Load per Bus Segment, C
BUS
400 pF
Capacitance for SDAI, SDAO, or SCL Pin, C
PIN
5 pF
Input Glitch Filter, t
SP
0 50 ns
SERIAL BUS TIMING
Table 2.
Parameter Description Min Typ Max Unit Test Conditions/Comments
f
SCLK
Clock frequency 400 kHz
t
BUF
Bus free time 1.3 µs
t
HD;STA
Start hold time 0.6 µs
t
SU;STA
Start setup time 0.6 µs
t
SU;STO
Stop setup time 0.6 µs
t
HD;DAT
SDA
1
hold time 300 900 ns
t
SU;DAT
SDA
1
setup time 100 ns
t
LOW
SCL low time 1.3 µs
t
HIGH
SCL high time 0.6 µs
t
R
2
SCL, SDA
1
rise time 20 300 ns
t
F
SCL, SDA
1
fall time 20 300 ns
t
OF
SCL, SDA
1
output fall time 20 + 0.1 × C
BUS
250 ns
1
SDAI and SDAO tied together.
2
t
R
= (V
IL(MAX)
– 0.15) to (V
IH3V3
+ 0.15) and t
F
= 0.9 V
DD
to (V
IL(MAX)
– 0.15); where V
IH3V3
= 2.1 V, and V
DD
= 3.3 V.
t
LOW
t
BUF
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
HIGH
t
R
t
F
t
SU;STO
PSSP
V
IH
V
IL
V
IH
V
IL
SCL
SDA
09312-002
Figure 2. Serial Bus Timing Diagram