Datasheet

Data Sheet ADM1075
Rev. B | Page 23 of 52
the PLIM pin, the relationship of V
DS
to V
PLIM
can be controlled.
The foldback voltage, V
FLB
, is the input to the current limit
reference selector block and is defined as
V
FLB
= 0.1/V
PLIM
The resistor divider should be designed to generate a V
FLB
voltage equal to I
SET
when the V
DS
of the FET (and thus V
PLIM
)
rises above the desired power level. If I
SET
= 1 V, V
PLIM
needs to
be 0.1 V at the point where constant power takes over (V
FLB
=
I
SET
). For example, to generate a 200 W constant power limit at
10 A current limit, the maximum V
DS
is required to be 20 V at
the current limit. Therefore, the resistor divider must be 200:1
to generate a 0.1 V PLIM voltage at V
DS
= 20 V. A s V
PLIM
continues to increase, the current limit reference follows V
FLB
because it is now the lowest voltage input to the current limit
reference selector block. This results in a reduction of the
current limit, and, therefore, the regulated load current. To
prevent complete current flow restriction, a clamp becomes
active when the current limit reference reaches 100 m V. T h e
current limit cannot drop below this level. This 200 W constant
power example is illustrated in terms of FET SOA and real
scope plots in Figure 49 and Figure 50.
When V
FLB
has control of the current limit reference, the
regulation current through the FET is
I
D
= V
FLB
/(Gain × R
SENSE
)
where I
D
is the external FET drain current, and Gain is the sense
amplifier gain.
I
D
= 0.1/(V
PLIM
× Gain × R
SENSE
)
I
D
= 0.1/(V
DS
× D × Gain × R
SENSE
)
where D is the resistor divider factor on PLIM.
Therefore, the FET power is calculated as
P
FET
= I
D
× V
DS
= 0.1/(D × Gain × R
SENSE
)
Because P
FET
does not have any dependency on V
DS
, it remains
constant. Therefore, the FET power for a given system can be
set by adjusting the divider (D) driving the PLIM pin.
The limits to the constant power system are when V
FLB
> I
SET
(or
1 V if V
ISET
> V
ISETRSTH
) or when V
FLB
< 100 mV (100 mV max
clamp on V
CLREF
). With an I
SET
voltage of 1 V, this gives a 10:1
foldback current range.
1000
100
10
1
0.1
0.1
1
10 100
1000
V
DS
(V)
I
D
(A)
09312-143
MAX 200W
POWER
DISSIPATION
60V × 3.33A = 200W
20V × 10A = 200W
1µs
10µs
100µs
1ms
10ms
DC
Figure 49. FET SOA
3,4
1,2
CURRENT LIMIT ADJUSTING
VIN
I
IN
V
DS
200W CONSTANT POWER
GATE
M1
09312-144
Figure 50. 200 W Constant Power Scope Plot, CH1 = VIN; CH2 = V
DS
;
CH3 = GATE; CH4 = System Current; M1 = FET Power
TIMER
The TIMER pin handles several timing functions with an
external capacitor, C
TIMER
. There are two comparator thresholds:
V
TIMERH
(1.0 V) and V
TIMERL
(0.05 V). The four timing current
sources are a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down,
and a 100 μA pull-down.
These current and voltage levels, together with the value of
C
TIMER
chosen by the user, determine the initial timing cycle
time, the fault current limit time, and the hot swap retry duty
cycle. The TIMER capacitor value is determined using the
following equation:
C
TIMER
= (t
ON
× 60 μA)/V
TIMERH
where t
ON
is the time that the FET is allowed to spend in
regulation. The choice of C
TIMER
is based on matching this time
with the SOA requirements of the FET. Foldback can be used
here to simplify selection.
When V
IN
is connected to the backplane supply, the internal
supply of the ADM1075 must be charged up. A very short time
later when the internal supply is fully up and above the undervolt-
age lockout voltage (UVLO), the device comes out of reset.
During this first short reset period, the GATE and TIMER pins
are both held low. The ADM1075 then goes through an initial