−48 V Hot Swap Controller and Digital Power Monitor with PMBus Interface ADM1075 Data Sheet FEATURES PRODUCT HIGHLIGHTS Constant power foldback for FET SOA protection Precision (<1.0%) current and voltage measurement Controls inrush and faults for negative supply voltages Suitable for wide input range due to internal shunt regulator 25 mV/50 mV full-scale sense voltage Fine tune current limit to allow use of standard sense resistor Soft start inrush current limit profiling 1% accurate UVH and OV pins, 1.
ADM1075 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Hot Swap Control Commands ................................................. 31 Applications ....................................................................................... 1 ADM1075 Information Commands ........................................ 31 Product Highlights ...........................................................................
Data Sheet ADM1075 Power Monitor Control Register ...............................................45 Read PIN_EXT Register............................................................. 49 Power Monitor Configuration Register ...................................45 Read EIN_EXT Register............................................................. 49 ALERT1 Configuration Register ...............................................46 Read VAUX Register............................................................
ADM1075 Data Sheet GENERAL DESCRIPTION The ADM1075 is a full feature, negative voltage, hot swap controller with constant power foldback and high accuracy digital current and voltage measurement that allows boards to be safely inserted and removed from a live −48 V backplane. The part provides precise and robust current limiting and protection against both transient and nontransient short circuits and overvoltage and undervoltage conditions.
Data Sheet ADM1075 SPECIFICATIONS VEE = −48 V, VSENSE = (VSENSE+ − VSENSE−) = 0 mV, shunt regulation current = 10 mA, TJ = −40°C to +105°C, unless otherwise noted. Table 1.
ADM1075 Parameter Constant Power Active Circuit Breaker Offset, VCBOS Severe Overcurrent Voltage Threshold, VSENSEOC Response Time Glitch Filter Duration Total Response Time ADM1075-2 ONLY (GAIN = 25) Hot Swap Sense Voltage Hot Swap Sense Voltage Current Limit, VSENSECL Constant Power Active Circuit Breaker Offset, VCBOS Severe Overcurrent Voltage Threshold, VSENSEOC1 Response Time Glitch Filter Duration Data Sheet Min 9.4 4.5 1.4 0.6 Typ 10 5 2 0.75 Max 11.0 5.7 2.6 0.
Data Sheet Parameter Total Response Time SOFT START SS Pull-Up Current, ISS Default VSENSECL Limit SS Pull-Down Current TIMER Timer Pull-Up Current (POR), ITIMERUPPOR Timer Pull-Up Current (OC Fault), ITIMERUPFLT Timer Pull-Down Current (Retry), ITIMERDNRT Timer Retry/OC Fault Current Ratio Timer Pull-Down Current (Hold), ITIMERDNHOLD Timer High Threshold, VTIMERH Timer Low Threshold, VTIMERL PLIM PLIM Active Threshold Input Current, IPLIM Minimum Current Clamp, VICLAMP DRAIN DRAIN Voltage at Which PWRGD
ADM1075 Data Sheet Parameter Leakage Current Min Input High Voltage, VIH Input Low Voltage, VIL Glitch Filter GPO2/ALERT2 PIN Output Low Voltage, VOL_GPO2 1.1 Typ Unit nA µA V V µs Test Conditions/Comments VGPO ≤ 2 V; GPO disabled VGPO = 14 V; GPO disabled Configured as CONV pin Configured as CONV pin Configured as CONV pin 0.4 1.5 100 1 V V nA µA IGPO = 1 mA IGPO = 5 mA VGPO ≤ 2 V; GPO disabled VGPO = 14 V; GPO disabled 0.4 1.
Data Sheet ADM1075 Parameter ADR PIN Address Set to 00 Input Current for Address 00 Address Set to 01 Address Set to 10 Address Set to 11 Input Current for Address 11 Min Typ 0 −40 135 −1 2.1 −22 150 3 SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL) Input High Voltage, VIH Input Low Voltage, VIL Output Low Voltage, VOL Input Leakage, ILEAK-PIN Nominal Bus Voltage, VDD Capacitive Load per Bus Segment, CBUS Capacitance for SDAI, SDAO, or SCL Pin, CPIN Input Glitch Filter, tSP Max Unit 0.
ADM1075 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VIN Pin to VEE UVL Pin to VEE UVH Pin to VEE OV Pin to VEE ADC_V Pin to VEE ADC_AUX Pin to VEE SS Pin to VEE TIMER Pin to VEE VCAP Pin to VEE ISET Pin to VEE SPLYGD Pin to VEE LATCH Pin to VEE RESTART Pin to VEE SHDN Pin to VEE PWRGD Pin to VEE DRAIN Pin to VEE SCL Pin to VEE SDAI Pin to VEE SDAO Pin to VEE ADR Pin to VEE GPO1/ALERT1/CONV Pin to VEE Rating −0.3 V to +14 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to +4 V −0.
Data Sheet ADM1075 VEE PLIM 6 23 SPLYGD VCAP 7 TOP VIEW (Not to Scale) 22 ADC_AUX ADC_V 8 21 PWRGD ISET 9 20 SCL SS 10 19 SDAI TIMER 11 18 SDAO LATCH 12 17 GPO2/ALERT2 ADR 13 16 GPO1/ALERT1/CONV SHDN 14 15 RESTART 21 SENSE– OV 1 PLIM 2 VCAP 3 ADC_V 4 ISET 5 20 VEE 19 SPLYGD ADM1075 18 ADC_AUX 17 PWRGD TOP VIEW (Not to Scale) SS 6 16 SCL TIMER 7 15 SDAI NOTES 1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE BOARD TO IMPROVE THERMAL DISSIPATION.
ADM1075 Data Sheet Pin No. TSSOP LFCSP 14 10 Mnemonic SHDN 15 11 RESTART 16 12 GPO1/ALERT1 /CONV 17 13 GPO2/ALERT2 18 19 20 21 14 15 16 17 SDAO SDAI SCL PWRGD 22 23 24 25 18 19 20 21 ADC_AUX SPLYGD VEE SENSE− 26 22 SENSE+ 27 23 GATE 28 24 VEE_G EPAD EPAD Description Drive this pin low to shut down the gate. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.
Data Sheet ADM1075 TYPICAL PERFORMANCE CHARACTERISTIC 10.0 5.0 4.5 9.5 4.0 RISING 9.0 8.5 3.0 UVLO (V) IIN (mA) 3.5 2.5 2.0 FALLING 8.0 7.5 1.5 7.0 1.0 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 6.0 –50 09312-005 0 –50 –35 –20 Figure 5. IIN vs. Temperature –5 10 25 40 55 TEMPERATURE (°C) 85 100 115 85 100 115 70 09312-008 6.5 0.5 Figure 8. UVLO vs. Temperature 14.0 10 13.5 9 12.5 IIN = 30mA 12.0 IIN = 5.5mA VGATE LOW (mV) VIN (V) 13.0 11.
ADM1075 Data Sheet 50 14 45 12 10 IGATE PULL-UP (µA) IGATE PULL-DOWN (mA) 40 8 6 4 35 30 25 20 15 10 2 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 09312-011 –35 0 2 6 4 8 14 12 10 VGATE (V) Figure 11. IGATE Pull-Down vs. Temperature 09312-014 5 0 –50 Figure 14. IGATE Pull-Up vs.
ADM1075 200 –1 180 –2 160 –3 –4 –5 –6 –7 140 120 100 80 60 –8 40 –9 20 –10 –50 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 –50 –35 –20 –5 10 25 40 55 70 85 100 115 100 115 100 115 TEMPERATURE (°C) 09312-020 PLIM THRESHOLD (mV) 0 09312-017 ITIMER POR PULL-UP (µA) Data Sheet Figure 20. PLIM Threshold vs. Temperature Figure 17. ITIMER POR Pull-Up vs.
ADM1075 Data Sheet 16 UVH 1000 14 UVL 12 RESTART TIME (s) UVx THRESHOLD (mV) 800 600 400 10 8 6 4 200 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 –40 09312-023 0 –50 –20 0 20 60 40 120 100 80 TEMPERATURE (°C) Figure 23. UVx Threshold vs. Temperature 09312-026 2 Figure 26. Restart Time vs.
ADM1075 50 1.8 45 1.6 40 1.4 35 VSENSECL (mV) 2.0 1.2 1.0 0.8 0.6 0.4 0.2 0 –50 –35 –20 –5 10 25 40 55 70 = 1.65V = 1.25V = 1.0V = 0.75V = 0.25V = 0.125V 85 100 ADM1075-2 +85°C ADM1075-2 +25°C ADM1075-2 –40°C ADM1075-1 +85°C ADM1075-1 +25°C ADM1075-1 –40°C 30 25 20 15 10 5 115 TEMPERATURE (°C) 0 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 VPLIM (V) Figure 29. Circuit Breaker Offset vs. Temperature, ADM1075-1 Figure 32. VSENSECL vs. PLIM 2.0 25 1.8 1.
ADM1075 Data Sheet 140 50 225% 45 120 SEVERE OC THRESHOLD (mV) SEVERE OC THRESHOLD (mV) 200% 40 35 150% 30 125% 25 20 15 10 225% 100 200% 80 150% 60 125% 40 ISET UNDEFINED IN GREY AREA 20 –35 –20 –5 10 25 40 55 70 85 100 115 TEMPERATURE (°C) 0 0.25 09312-035 0 –50 0.45 0.65 0.85 1.05 1.25 1.45 09312-237 5 1.65 ISET (V) Figure 38. Severe OC Threshold vs. ISET, ADM1075-2 Figure 35. Severe OC Threshold vs. Temperature, ADM1075-1, ISET = 1.
Data Sheet 00 DECODE ADM1075 10 DECODE 11 DECODE 01 DECODE 3.0 2.5 1.5 1.0 0.5 0 –25 –20 –15 –10 –5 IADR (µA) 0 5 09312-041 VADR (V) 2.0 Figure 41. VADR vs. IADR Rev.
ADM1075 Data Sheet THEORY OF OPERATION When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system.
Data Sheet ADM1075 –48V RTN VIN Rb1 = 100kΩ Rb2 = 640Ω ADM1075 Q1 GATE Ib = 6µA TO 33µA 10.3V (5.5mA) 11V RDROP = 15Ω –48V SENSE+ BIAS CURRENT CLOAD SENSE– VIN 1µF VEE GATE VEE ADM1075 Q1 SENSE+ Figure 45. Connection of Multiple Sense Resistors to SENSE± Pins RSENSE CURRENT LIMIT REFERENCE 09312-137 SENSE– VEE Figure 43. Wide Input Supply Range CURRENT SENSE INPUTS The load current is monitored by measuring the voltage drop across an external sense resistor, RSENSE.
ADM1075 Data Sheet Assuming VISET equals the voltage on the ISET pin, the resistor divider should be sized to set the ISET voltage as follows: V FLB SS 1V VISET = (VSENSE × 50) for ADM1075-1 or VISET = (VSENSE × 25) for ADM1075-2 ISET where VSENSE is the sense voltage limit. The VCAP rail can also be used as the pull-up supply for setting the I2C address. The VCAP pin should not be used for any other purpose.
Data Sheet ADM1075 the PLIM pin, the relationship of VDS to VPLIM can be controlled. The foldback voltage, VFLB, is the input to the current limit reference selector block and is defined as 1000 1µs 10µs 100 VFLB = 0.1/VPLIM ID (A) 100µs 1ms 10 MAX 200W POWER DISSIPATION 10ms 1 DC 20V × 10A = 200W 60V × 3.33A = 200W 0.1 0.
ADM1075 Data Sheet timing cycle. The TIMER pin is pulled up with 3 μA. When the TIMER reaches the VTIMERH threshold (1.0 V), the first portion of the initial cycle is complete. The 100 μA current source then pulls down the TIMER pin until it reaches VTIMERL (0.05 V). The initial cycle duration is related to CTIMER by the following equation: t INITIAL = VTIMERH × CTIMER (VTIMERH / VTIMERL ) × CTIMER + 3 μA 100 μA For example, a 470 nF capacitor results in a power-up delay of approximately 160 ms.
Data Sheet ADM1075 the voltage connected to the UVL pin falls below 0.9 V, and the gate is shut down using the 10 mA pull-down device. The fault is cleared after UVH pin rises above 1.0 V. Similarly, when an overvoltage event occurs and the voltage on the OV pin exceeds 1 V, the gate is shut down using the 10 mA pull-down device. SPLYGD The SPLYGD output indicates when the input supply is within the programmed voltage window. This is an open-drain output.
ADM1075 Data Sheet The ADM1075 features a method of detecting a shorted pass FET. The FET health status can be used to generate an alert on the GPO1/ALERT1/CONV and GPO2/ALERT2 pins. By default, at power-up, an alert is generated on GPO1/ALERT1/CONV if the FET health status indicates a bad FET is present. FET health is considered bad if all of the following conditions are true: • • • The ADM1075 is holding the FET off, for example, during the initial power-on cycle time.
Data Sheet ADM1075 be powered from the secondary side and can provide power across the isolation barrier via the integrated dc-to-dc converter. Therefore, the ADuM5404 can be used to power the primary side of the ADuM1250 if both are used on the board. Some extra care is required if using the ADuM5404 to power the ADuM3200. If the power at the secondary side is enabled by the ADM1075, the isoPower solution may not work.
ADM1075 Data Sheet PMBus INTERFACE The I2C bus is a common, simple serial bus used by many devices to communicate. It defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules. SMBus is based on I2C and aims to provide a more robust and fault-tolerant bus. Functions such as bus timeout and packet error checking are added to help achieve this robustness, along with more specific definitions of the bus messages used to read and write data to devices on the bus.
Data Sheet ADM1075 SMBus MESSAGE FORMATS R = read bit W = write bit A = acknowledge bit (0) A = acknowledge bit (1) Figure 55 to Figure 63 show all the SMBus protocols supported by the ADM1075, along with the PEC variant. In these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the ADM1075 is driving the bus. “A” represents the ACK (acknowledge) bit.
ADM1075 S Data Sheet SLAVE ADDRESS W DATA BYTE 1 S A DATA BYTE 2 A W SLAVE ADDRESS DATA BYTE 1 COMMAND CODE A DATA BYTE N A Sr COMMAND CODE DATA BYTE 2 A A SLAVE ADDRESS DATA BYTE N A BYTE COUNT = N A A BYTE COUNT = N A P R A PEC A P 09312-056 A A R SLAVE ADDRESS A Sr MASTER TO SLAVE SLAVE TO MASTER Figure 61.
Data Sheet ADM1075 HOT SWAP CONTROL COMMANDS POWER_CYCLE Command OPERATION Command The POWER_CYCLE command can be used to request that the ADM1075 be turned off for ~10 seconds and then back on. This command can be useful if the processor that controls the ADM1075 is also powered off when the part is turned off. This command allows the processor to request that the ADM1075 turn off and back on again as part of a single command.
ADM1075 Data Sheet All warnings in the ADM1075 are generated by the power monitor sampling voltage and current and then comparing these measurements to the threshold values set by the various limit commands. A warning has no effect on the hot swap controller, but it may generate an SMBAlert on one or both of the GPOx/ALERTx output pins. When a fault or warning status bit is set, it always means that the status condition—fault or warning—is active or was active at some point in the past.
Data Sheet ADM1075 These registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the ADM1075.
ADM1075 Data Sheet VAUX_OV_WARN_LIMIT and VAUX_UV_WARN_LIMIT Commands The PIN_OP_WARN_LIMIT command is used to set the overpower (OP) threshold for the power measurement register. The sense resistor value used in the calculations to obtain the coefficients is expressed in milliohms. The m coefficients are defined as 2-byte twos complement numbers in the PMBus standard; therefore, the maximum positive value that can be represented is 32,767.
Data Sheet ADM1075 Table 7. PMBus Conversion to Real-World Coefficients Coefficient m b R Voltage (V) 27,169 0 −1 ADM1075-1 806 × RSENSE 20,475 −1 Current (A) ADM1075-2 404 × RSENSE 20,475 −1 Example 3 The READ_VIN command returns a direct format value of 1726. The ADC_V pin is shorted to the OV pin, which is connected to the input supply via an 820 kΩ/11 kΩ resistor divider. To convert this value to the input voltage, use Equation 2 X = 1/27,169 × (1726 × 101 – 0) X = 0.635 V This corresponds to 0.
ADM1075 Data Sheet ADM1075 ALERT PIN BEHAVIOR The ADM1075 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. FAULTS AND WARNINGS A PMBus fault on the ADM1075 is always generated due to an analog event and causes a change in state in the hot swap output, turning it off.
Data Sheet ADM1075 SMBus ALERT RESPONSE ADDRESS 3. The SMBus alert response address (ARA) is a special address that can be used by the bus host to locate any devices that need to talk to it. A host typically uses a hardware interrupt pin to monitor the SMBus alert pins of a number of devices. When the host interrupt occurs, the host issues a message on the bus using the SMBus receive byte or receive byte with PEC protocol. The special address used by the host is 0x0C.
ADM1075 Data Sheet PMBus COMMAND REFERENCE Register addresses are in hexadecimal format. Table 8.
Data Sheet ADM1075 REGISTER DETAILS OPERATION COMMAND REGISTER Address: 0x01, Reset: 0x00, Name: OPERATION Table 9. Bit Descriptions for OPERATION Bits 7 Bit Name ON Settings 0 1 [6:0] RESERVED Description Hot swap enable. Hot swap output disabled. Hot swap output enabled. Always reads as 0000000.
ADM1075 Data Sheet PIN OP WARN LIMIT REGISTER Address: 0x6B, Reset: 0x7FFF, Name: PIN_OP_WARN_LIMIT Table 14. Bit Descriptions for PIN_OP_WARN_LIMIT Bits 15 [14:0] Bit Name RESERVED PIN_OP_WARN_LIMIT Settings Description Always reads as 0. Overpower threshold for the PMBus power measurement, expressed in ADC codes.
Data Sheet Bits 13 Bit Name INPUT_STATUS ADM1075 Settings 0 1 12 MFR_STATUS 0 1 11 PGB_STATUS 0 1 [10:8] [7:0] RESERVED STATUS_BYTE Description Live register. There are no active status bits to be read by STATUS_INPUT. There are one or more active status bits to be read by STATUS_INPUT. Live register. There are no active status bits to be read by STATUS_MFR_SPECIFIC. There are one or more active status bits to be read by STATUS_MFR_SPECIFIC. Live register.
ADM1075 Bits 4 Bit Name VIN_UV_FAULT Data Sheet Settings 0 1 [3:1] 0 RESERVED PIN_OP_WARN 0 1 Description Latched register. No undervoltage detected on the UVx pin. An undervoltage was detected on the UVx pin. Always reads as 000. Latched register. No overpower condition on the input supply detected by the power monitor. An overpower condition on the input supply was detected by the power monitor.
Data Sheet ADM1075 READ EIN REGISTER Address: 0x86, Reset: 0x06, 0x0000, 0x00, 0x000000, Name: READ_EIN Table 20. Bit Descriptions for READ_EIN Byte [0] Bit Name BYTE_COUNT [2:1] ENERGY_COUNT [3] ROLLOVER_COUNT [6:4] SAMPLE_COUNT Settings Description Always reads as 0x06, the number of data bytes that the block read command should expect to read. Energy accumulator value in direct format. Byte 2 is the high byte, and Byte 1 is the low byte.
ADM1075 Data Sheet MANUFACTURING ID REGISTER Address: 0x99, Reset: 0x03 + ASCII “ADI”, Name: MFR_ID Table 25. Bit Descriptions for MFR_ID Byte 0 Bit Name BYTE_COUNT 1 2 3 CHARACTER1 CHARACTER2 CHARACTER3 Settings Description Always reads as 0x03, the number of data bytes that the block read command should expect to read. Always reads as 0x41 = “A”. Always reads as 0x44 = “D”. Always reads as 0x49 = “I”.
Data Sheet ADM1075 PEAK VIN REGISTER Address: 0xD1, Reset: 0x0000, Name: PEAK_VIN (writing 0x0000 clears the peak value) Table 29. Bit Descriptions for PEAK_VIN Bits [15:12] [11:0] Bit Name RESERVED PEAK_VIN Settings Description Always reads as 0000. Returns the peak VIN voltage since the register was last cleared.
ADM1075 Data Sheet ALERT1 CONFIGURATION REGISTER Address: 0xD5, Reset: 0x8000, Name: ALERT1_CONFIG Table 33. Bit Descriptions for ALERT1_CONFIG Bits 15 Bit Name FET_HEALTH_BAD_EN1 Settings Description 0 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Default. Disables generation of SMBAlert when the VAUX_UV_WARN bit is set. Generates SMBAlert when the VAUX_UV_WARN bit is set. HS_INLIM_EN1 0 0x0 Default.
Data Sheet Bits 3 Bit Name PIN_OP_WARN_EN1 ADM1075 Settings Description 0 1 [2:1] 10 11 0 0x0 RW 0x0 RW Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW Default. GPO1 is configured to generate SMBAlerts. GPO1 can be used a general-purpose digital output pin. The GPO1_INVERT bit is used to change the output state. GPO1 is configured as a convert (CONV) input pin. This is digital comparator mode.
ADM1075 Bits 7 Bit Name VIN_UV_WARN_EN2 Data Sheet Settings Description 0 1 6 1 5 1 4 1 3 1 [2:1] 10 11 0 0x0 RW 0x0 RW 0x2 RW 0x0 RW Reset 0x0 0x0 Access R RW Reset 0x00 0x0 Access R RW GPO2 is configured to generate SMBAlerts. GPO2 can be used a general-purpose digital output pin. The GPO2_INVERT bit is used to change the output state. Default. GPO2 is configured as a retry fail output. This is digital comparator mode.
Data Sheet Bits 4 Bit Name IOUT_WARN2_OC_SELECT ADM1075 Settings 0 1 [3:2] OC_TRIP_SELECT 00 01 10 11 [1:0] OC_FILT_SELECT 00 01 10 11 Description Sets IOUT Warning 2 limit to OC or UC. Configures IOUT_WARN2_LIMIT as an undercurrent threshold Configured IOUT_WARN2_LIMIT as an overcurrent threshold Sets severe OC trip threshold. 125%. 150%. Default. 200%. 225%. Sets severe OC filter time. 200 ns. Default. 900 ns. 10.7 µs. 57 µs.
ADM1075 Data Sheet READ VAUX REGISTER Address: 0xDD, Reset: 0x0000, Name: READ_VAUX Table 40. Bit Descriptions for READ_VAUX Bits [15:12] [11:0] Bit Name RESERVED READ_VAUX Settings Description Always reads as 0000. Output voltage from the ADC_AUX pin measurement, expressed in ADC codes. Reset 0x0 0x0 Access R R Reset 0x0 0xFFF Access R RW Reset 0x0 0x0 Access R RW Reset 0x0 Access R 0x0 R 0x0 R VAUX OV WARN LIMIT REGISTER Address: 0xDE, Reset: 0x0FFF, Name: VAUX_OV_WARN_LIMIT Table 41.
Data Sheet ADM1075 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 8° 0° 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 64. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 0.30 0.25 0.18 PIN 1 INDICATOR 22 0.50 BSC 1 21 EXPOSED PAD 3.40 3.30 SQ 3.20 15 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 7 14 8 BOTTOM VIEW 0.05 MAX 0.
ADM1075 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09312-0-4/13(B) Rev.