Datasheet

REV. 0–2–
ADM1070–SPECIFICATIONS
Parameter Min Typ Max Unit Test Conditions
BOARD SUPPLY
(not connected directly to device)
Maximum Voltage Range –200 –48 –20 V Limited by Voltage Capability of
External Components*
Typical Operating Voltage Range –77 –48 –36 V R
DROP
= 16 kΩ, R1/R2 = 40*
VIN PIN––SHUNT REGULATOR
Operating Supply Voltage Range, V
SS
11.5 12.3 13 V I
SS
= 1.5 mA to 4.25 mA
Quiescent Supply Current, I
SS
0.4 0.85 1.3 mA V
SS
= 11.5 V
Maximum Shunt Supply Voltage, V
SS
12.5 14 V I
SS
= 20 mA
Undervoltage Lockout, V
LKO
7 8.5 10.5 V
UV/OV PIN––UNDERVOLTAGE AND
OVERVOLTAGE DETECTION
Undervoltage Falling Threshold, V
UVF
0.81 0.86 0.91 V
Undervoltage Rising Threshold, V
UVR
0.86 0.91 0.96 V
Undervoltage Hysteresis, V
UVH
45 mV
Overvoltage Falling Threshold, V
OVF
1.85 1.93 2.01 V
Overvoltage Rising Threshold, V
OVR
1.89 1.97 2.05 V
Overvoltage Hysteresis V
OVH
–45 mV
Power-On Reset Delay, t
POR
1.10 1.70 2.30 ms TIMER Pin Tied to V
EE
(V
UVR
< UV/OV < V
OVF
)
0.90 1.21 1.51 ms C
TIMER
= 470 pF
(V
UVR
< UV/OV < V
OVF
)
Voltage Fault Filter Time (UV/OV Out of
Voltage
Window), t
FLT
1.10 1.70 2.30 ms TIMER Pin Tied to V
EE
(V
UVR
< UV/OV < V
OVF
)
0.90 1.21 1.51 ms C
TIMER
= 470 pF
(V
UVR
< UV/OV < V
OVF
)*
Input Current, I
VMON
1.0 µA
GATE PIN––FET DRIVER
Maximum Gate Voltage, V
GMAX
11 12 13 V I
GATE
= –1 µA
Minimum Gate Voltage, V
GMIN
050mVI
GATE
= 1 µA
Pull-Up Current, I
GUP
–20 –40 –55 µAV
GATE
= 0 V to 9 V, V
SENSE
= 0
Pull-Down Current, I
GDP
10 30 mA V
GATE
= V
SS
Hold-off Impedance, R
GOFF
10 k⍀ V
GATE
< 2 V, V
SS
> 11 V
30 k⍀ V
GATE
< 2 V, V
SS
> 2 V
SENSE PIN––CURRENT SENSE
Analog Current Limit Voltage (Rising),V
LIM
90 100 110 mV I
GATE
= 0 µA to –15 µA
Circuit Breaker Limit Voltage (Rising) 75 88 100 mV
Circuit Breaker Limit Voltage (Rising) –12 mV
(With Respect to V
LIM
), V
LIMITON
Circuit Breaker Limit Voltage (Falling) 60 79 95 mV
Circuit Breaker Limit Voltage (Falling) –21 mV
(With Respect to V
LIM
), V
LIMITOFF
Fast Current Limit Voltage 107 126 145 mV
Fast Current Limit Voltage 26 mV
(With Respect to V
LIM
)
Control Loop Transconductance, 1.5 2.75 4 µA/mV I
GATE
< ⫾30 µA, T
A
= 25°C
(dI
GATE
/dV
SENSE
)
Maximum Current Limit On Time, t
LIMITON
10 14 18 ms TIMER Pin Tied to V
EE
(V
UVR
< UV/OV < V
OVF
)
7.4 9.9 12.4 ms C
TIMER
= 470 pF
(V
UVR
< UV/OV < V
OVF
)*
Current Limit PWM Off Time 320 450 580 ms TIMER Pin Tied to V
EE
(V
UVR
< UV/OV < V
OVF
)*
240 320 400 ms C
TIMER
= 470 pF
(V
UVR
< UV/OV < V
OVF
)*
Current Limit PWM Duty Cycle 3 % (Typical Only)
Number of Consecutive PWM Retry Cycles 7 (Typical Only)
(V
DD
= 0 V, V
EE
= –48 V, R
DROP
= 16 k⍀, T
A
= –40ⴗC to +85ⴗC, unless other-
wise noted.)