Datasheet
ADM1066
Rev. E | Page 7 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, V
IH
2.0 V Maximum V
IN
= 5.5 V
Input Low Voltage, V
IL
0.8 V Maximum V
IN
= 5.5 V
Input High Current, I
IH
−1 μA V
IN
= 5.5 V
Input Low Current, I
IL
1 μA V
IN
= 0 V
Input Capacitance 5 pF
Programmable Pull-Down
Current, I
PULL-DOWN
20 μA VDDCAP = 4.75 V, T
A
= 25°C, if known logic state is required
SERIAL BUS DIGITAL INPUTS
(SDA, SCL)
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.8 V
Output Low Voltage, V
OL
2
0.4 V I
OUT
= −3.0 mA
SERIAL BUS TIMING
3
Clock Frequency, f
SCLK
400 kHz
Bus Free Time, t
BUF
1.3 μs
Start Setup Time, t
SU;STA
0.6 μs
Stop Setup Time, t
SU;STO
0.6 μs
Start Hold Time, t
HD;STA
0.6 μs
SCL Low Time, t
LOW
1.3 μs
SCL High Time, t
HIGH
0.6 μs
SCL, SDA Rise Time, t
R
300 ns
SCL, SDA Fall Time, t
F
300 ns
Data Setup Time, t
SU;DAT
100 ns
Data Hold Time, t
HD;DAT
5 ns
Input Low Current, I
IL
1 μA V
IN
= 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 μs
1
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2
Specification is not production tested but is supported by characterization data at initial product release.
3
Timing specifications are guaranteed by design and supported by characterization data.