Datasheet
ADM1064
Rev. D | Page 7 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04633-003
NOTES
1. NC = NO CONNECT.
2
. THE LFCSP HAS AN EXPOSED PAD ON THE BOTTOM.
THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS
PAD SHOULD BE SOLDERED TO THE BOARD FOR
IMPROVED MECHANIC
A
L STABILITY.
ADM1064
TOP VIEW
(Not to Scale)
GND
40
VDDCAP
39
AUX1
38
AUX2
37
SDA
36
SCL
35
A1
34
A0
33
VCCP
32
PDOGND
31
AGND
11
REFGND
12
REFIN
13
REFOUT
14
NC
15
NC
16
NC
17
NC
18
NC
19
NC
20
V
X1
1
V
X2
2
V
X3
3
V
X4
4
V
X5
5
V
P1
6
V
P2
7
V
P3
8
V
P4
9
VH
10
PDO1
30
PDO2
29
PDO3
28
PDO4
27
PDO5
26
PDO6
25
PDO7
24
PDO8
23
PDO9
22
PDO10
21
PIN 1
INDICATOR
04633-004
NC = NO CONNECT
NC
48
PDOGND
38
VDDCAP
46
VCCP
39
AUX1
45
AUX2
44
GND
47
SDA
43
SCL
42
NC
37
A1
41
A0
40
Figure 3. LFCSP Pin Configuration
NC
13
AGND
14
REFGND
15
REFIN
16
REFOUT
17
NC
18
NC
19
NC
20
NC
21
NC
22
NC
23
NC
24
NC 1 NC36
V
X1 2
V
X2 3
V
X3 4
V
X4 5
V
X5 6
V
P1 7
V
P2 8
V
P3 9
V
P4 10
VH
11
NC
12
PDO135
PDO234
PDO333
PDO432
PDO531
PDO630
PDO729
PDO828
PDO927
PDO10
26
NC
25
ADM1064
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No.
LFCSP
1
Mnemonic
TQFP
Description
15 to
20
1, 12, 13,
18 to 25,
36, 37, 48
NC No Connection.
1 to 5 2 to 6
VX1 to VX5
(VXx)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
6 to 9 7 to 10
VP1 to VP4
(VPx)
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a
supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and
from 0.573 V to 1.375 V.
10 11 VH
High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11 14 AGND
2
Ground Return for Input Attenuators.
12 15 REFGND
Ground Return for On-Chip Reference Circuits.
13 16 REFIN
Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
14 17 REFOUT
2
Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be
connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
21 to
30
26 to 35
PDO10 to
PDO1
Programmable Output Drivers.
31 38 PDOGND
2
Ground Return for Output Drivers.
32 39 VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND. A 10 μF capacitor is recommended for this purpose.
33 40 A0
Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1
Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL
SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
36 43 SDA
SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
37 44 AUX2 Auxiliary, Single-Ended ADC Input.