Datasheet

ADM1064
Rev. D | Page 5 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
Conversion Time 0.44 ms One conversion on one channel
84 ms All 12 channels selected, averaging enabled
Offset Error ±2 LSB V
REFIN
= 2.048 V
Input Noise 0.25 LSB rms Direct input (no attenuator)
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current
0.25 mV Sinking current
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance 500 kΩ
V
OH
11 12.5 14 V I
OH
= 0 μA
10.5 12 13.5 V I
OH
= 1 μA
I
OUTAVG
20 μA 2 V < V
OH
< 7 V
Standard (Digital Output) Mode
(PDO1 to PDO10)
V
OH
2.4 V V
PU
(pull-up to VDDCAP or VPx) = 2.7 V, I
OH
= 0.5 mA
4.5 V V
PU
to VPx = 6.0 V, I
OH
= 0 mA
V
PU
− 0.3 V V
PU
≤ 2.7 V, I
OH
= 0.5 mA
V
OL
0 0.50 V I
OL
= 20 mA
I
OL
2
20 mA Maximum sink current per PDOx pin
I
SINK
2
60 mA Maximum total sink for all PDOx pins
R
PULL-UP
16 20 29 kΩ Internal pull-up
I
SOURCE
(VPx)
2
2 mA
Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
Three-State Output Leakage Current 10 μA V
PDO
= 14.4 V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, V
IH
2.0 V Maximum V
IN
= 5.5 V
Input Low Voltage, V
IL
0.8 V Maximum V
IN
= 5.5 V
Input High Current, I
IH
−1 μA V
IN
= 5.5 V
Input Low Current, I
IL
1 μA V
IN
= 0
Input Capacitance 5 pF
Programmable Pull-Down Current, I
PULL-DOWN
20 μA
VDDCAP = 4.75 V, T
A
= 25°C, if known logic state is
required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V
IH
2.0 V
Input Low Voltage, V
IL
0.8 V
Output Low Voltage, V
OL
2
0.4 V I
OUT
= −3.0 mA
SERIAL BUS TIMING
3
Clock Frequency, f
SCLK
400 kHz
Bus Free Time, t
BUF
1.3 μs
Start Setup Time, t
SU;STA
0.6 μs
Stop Setup Time, t
SU;STO
0.6 μs
Start Hold Time, t
HD;STA
0.6 μs
SCL Low Time, t
LOW
1.3 μs
SCL High Time, t
HIGH
0.6 μs
SCL, SDA Rise Time, t
R
300 ns
SCL, SDA Fall Time, t
F
300 ns