Datasheet

ADM1063
Rev. C | Page 6 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
SERIAL BUS TIMING
4
Clock Frequency, f
SCLK
400 kHz
Bus Free Time, t
BUF
1.3 μs
Start Setup Time, t
SU;STA
0.6 μs
Stop Setup Time, t
SU;STO
0.6 μs
Start Hold Time, t
HD;STA
0.6 μs
SCL Low Time, t
LOW
1.3 μs
SCL High Time, t
HIGH
0.6 μs
SCL, SDA Rise Time, t
R
300 ns
SCL, SDA Fall Time, t
F
300 ns
Data Setup Time, t
SU;DAT
100 ns
Data Hold Time, t
HD;DAT
5 ns
Input Low Current, I
IL
1 μA V
IN
= 0 V
SEQUENCING ENGINE TIMING
State Change Time 10 μs
1
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2
All temperature sensor measurements are taken with round-robin loop enabled and at least one other voltage input being measured.
3
Specification is not production tested but is supported by characterization data at initial product release.
4
Timing specifications are guaranteed by design and supported by characterization data.