Datasheet

ADM1060
Rev. B | Page 18 of 52
WATCHDOG FAULT DETECTOR
The ADM1060 has a watchdog fault detector. This can be used
to monitor a processor clock to ensure normal operation. The
detector monitors the WDI pin, expecting a low-to-high or
high-to-low transition within a preprogrammed period. The
watchdog timeout period can be programmed from 200 ms to a
maximum of 12.8 sec.
If no transition is detected, two signals are asserted. One is a
latched high signal, indicating a fault has occurred. The other
signal is a low-high-low pulse that can be used as a RESET sig-
nal for a processor core. The width of this pulse can be
programmed from 10 µs to a maximum of 10 ms. These two
watchdog signals can be selected as inputs to each of the PLBs
(see the PLBA section). They can also be inverted, if required;
for example, if a high-low-high pulse were required by a proces-
sor to reset. Thus, a fault on the watchdog can be used to
generate a pulsed or latched output on any or all of the nine
PDOs.
The latched signal can be cleared low by reading LATF1, then
LATF2 across the SMBus interface (see the Fault Registers sec-
tion). The RAM register list and the bit map for the watchdog
fault detector are shown below.
Table 20. Watchdog Fault Detector Registers
Hex Address Table Name Default Power-On Value Description
9C Table 21 WDCFG 0x00 Program Length Watchdog Timeout and Length of Pulsed Output
Table 21. WDCFG Register 0x9C (Power-On Default 0x00)
Bit Name R/W Description
7−5 Reserved R/W Unused
PULS1 PULS0 Pulse Length Selected (µs)
0 0 10
0 1 100
1 0 1,000
4−3 PULS1−PULS0 R/W
Length of Pulse Output once
the Watchdog Detector has
Timed Out
1 1 10,000
PER2 PER1 PER0 Watchdog Timeout Selected (ms)
0 0 0 Disabled
0 0 1 200
0 1 0 400
0 1 1 800
1 0 0 1,600
1 0 1 3,200
1 1 0 6,400
2–0 PER2−PER0 R/W Watchdog Timeout Period
1 1 1 12,800