Datasheet
ADL5315
Rev. 0 | Page 12 of 20
TRANSLINEAR LOG AMP INTERFACING
The mirror current output, IOUT, of the ADL5315 is designed
to interface directly to an Analog Devices translinear
logarithmic amplifier, such as the
AD8304, AD8305, or
ADL5306.
Figure 24 shows the basic connections necessary for interfacing
the ADL5315 to the AD8305. In this configuration, the designer
can use the full current mirror range of the ADL5315 for high
accuracy power monitoring.
The measured rms noise voltage at the output of the AD8305 vs.
the input current is shown in
Figure 23, both for the AD8305 by
itself and in cascade with the ADL5315. The relatively low noise
produced by the ADL5315, combined with the additional noise
filtering inherent in the frequency response characteristics of
the AD8305, results in minimal degradation to the noise
performance of the AD8305.
Careful consideration should be made to the layout of the
circuit board in this configuration. Leakage current paths in the
board itself could lead to measurement errors at the output of
the translinear log amp, particularly when measuring the low
end of the ADL5315’s dynamic range. It is recommended that
when designing such an interface that a guard potential be used
to minimize this leakage. This can be done by connecting the
translinear log amp’s VSUM pin to the NC pin of the ADL5315,
with the VSUM guard trace running on both sides of the IOUT
trace. Additional details on using VSUM can be found in the
AD8304 or AD8305 data sheets. The VSET pin of the ADL5315
can be used in a similar fashion to guard the INPT trace.
5.5m
0
1n
1m
I
INPT
(A)
NOISE (V rms)
5.0m
4.5m
4.0m
3.5m
3.0m
2.5m
2.0m
1.5m
1.0m
0.5m
10n 100n 1μ 10μ 100μ
05694-012
AD8305 AND
ADL5315
AD8305 ONLY
Figure 23. Measured RMS Noise of AD8305 vs. AD8305
Cascaded with ADL5315
VOLTAGE
REFERENCE
CURRENT
LIMITING
COMM
VSET NC
INPT
DATA PATH
AD8305 INPUT
COMPENSATION
NETWORK
I
PD
CURRENT
MIRROR
1:1
ADL5315
4
2 7
SREF
3
1
6
VPOS
PIN
20kΩ
5
RLIM
R
LIM
I
LIM =
1mA – 16mA
3V TO 12V
8
IOUT
I
PD
TIA
1
2
3
4
11
SCAL
12
VOUT
10
BFIN
9
VLOG
5
VSUM
6
VNEG
7
VNEG
8
VPOS
15
COMM
16
COM
M
14
COMM
13
COMM
AD8305
VRDZ
VREF
IREF
INPT
OUTPUT
V
OUT
= 0.2 × LOG
10
(I
PDM
/1nA)
200kΩ
2kΩ
4.7nF
1nF
1kΩ
0.1μF
05694-011
C
SET
V
POS
R
LIM
= 48V
I
LIM
– 3kΩ
Figure 24. Interfacing the ADL5315 to the AD8305 for High Accuracy PIN Power Monitoring