Datasheet

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0.5 Ω CMOS, 1.8 V to 5.5 V,

Dual SPDT/2:1 Mux, Mini LFCSP

ADG854

Rev. 0

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FEATURES

0.8 Ω typical on resistance

Less than 1 Ω maximum on resistance at 85°C

1.8 V to 5.5 V single supply

High current carrying capability: 300 mA continuous

Rail-to-rail switching operation

Fast-switching times: <17 ns

Typical power consumption: <0.1 μW

1.30 mm × 1.60 mm mini LFCSP

APPLICATIONS

Cellular phones

PDAs

MP3 players

Power routing

Battery-powered systems

PCMCIA cards

Modems

Audio and video signal routing

Communication systems

FUNCTIONAL BLOCK DIAGRAM

S1A

S1B

IN1

IN2

ADG854

SWITCHES SHOWN FOR

A LOGIC 1 INPUT

S2A

S2B

07087-001

Figure 1.

GENERAL DESCRIPTION

The ADG854 is a low voltage CMOS device containing two

independently selectable single-pole, double-throw (SPDT)

switches. This device offers ultralow on resistance of <1 Ω over

the full temperature range. The ADG854 is fully specified for

5.5 V and 3.3 V supply operation.

Each switch conducts equally well in both directions when on

and has an input signal range that extends to the supplies. The

ADG854 exhibits break-before-make switching action.

The ADG854 is available in a 1.3 mm × 1.6 mm 10-lead

mini LFCSP.

PRODUCT HIGHLIGHTS

1. <1 Ω over full temperature range of –40°C to +85°C.

2. Single 1.8 V to 5.5 V operation.

3. Compatible with 1.8 V CMOS logic.

4. High current handling capability: 300 mA continuous

current per channel.

5. Low THD + N: 0.08% typical.

6. 1.30 mm × 1.60 mm mini LFCSP.

Summary of content (16 pages)

PAGE 1
0.5 Ω CMOS, 1.8 V to 5.5 V, Dual SPDT/2:1 Mux, Mini LFCSP ADG854 FEATURES FUNCTIONAL BLOCK DIAGRAM 0.8 Ω typical on resistance Less than 1 Ω maximum on resistance at 85°C 1.8 V to 5.5 V single supply High current carrying capability: 300 mA continuous Rail-to-rail switching operation Fast-switching times: <17 ns Typical power consumption: <0.1 μW 1.30 mm × 1.
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ADG854 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Pin Configurations and Function Description..............................6 Functional Block Diagram ..............................................................
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ADG854 SPECIFICATIONS VDD = 4.2 V to 5.5V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON +25°C 0.8 0.85 0.02 −40°C to +85°C Unit 0 to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 1 0.04 On Resistance Flatness, RFLAT (ON) 0.17 0.
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ADG854 VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, ∆RON +25°C 1.3 1.5 0.03 −40°C to +85°C Unit 0 to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 1.7 0.05 On Resistance Flatness, RFLAT (ON) 0.48 0.
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ADG854 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND Analog Inputs 1 Digital Inputs1 Peak Current per Channel, S or D Continuous Current per Channel, S or D Operating Temperature Range Storage Temperature Range Junction Temperature 10-Lead Mini LFCSP θJA Thermal Impedance, 3-Layer Board Reflow Soldering, Pb-Free Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.
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ADG854 9 S2A 8 D2 VDD 6 7 S2B 07087-002 1 S1A TOP VIEW (Not to Scale) IN1 4 S1B 3 ADG854 IN2 5 D1 2 10 GND PIN CONFIGURATION AND FUNCTION DESCRIPTION Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1, 3, 7, 9 2, 8 4 5 6 10 Mnemonic S1A, S1B, S2B, S2A D1, D2 IN1 IN2 VDD GND Description Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Logic Control Input. Logic Control Input. Most Positive Power Supply Potential.
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ADG854 TYPICAL PERFORMANCE CHARACTERISTICS 0.9 1.2 VDD = 3.3V TA = 25°C 0.8 TA = +85°C 1.0 ON RESISTANCE (Ω) 0.6 0.5 0.4 VDD VDD VDD VDD 0.3 0.2 = 4.2V = 4.5V = 5.0V = 5.5V 07087-003 0 1 TA = –40°C 0.6 0.4 0.2 0.1 0 TA = +25°C 0.8 3 2 4 5 07087-006 ON RESISTANCE (Ω) 0.7 0 6 0 0.5 1.0 VD, VS (V) 1.5 2.0 2.5 3.0 VD, VS (V) Figure 3. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V Figure 6. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V 1.1 1.
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ADG854 70 0 VDD = 5V –10 TA = 25°C VDD = 5V, 3.3V –20 50 ATTENUATION (dB) 40 30 VDD = 3V 20 VDD = 2.5V 07087-009 0 1 2 3 –40 –50 –60 –70 10 0 –30 4 5 –80 –90 0.1 6 1 SOURCE VOLTAGE (V) 10 FREQUENCY (MHz) 100 07087-012 CHARGE INJECTION (pC) 60 1k Figure 12. Off Isolation vs. Frequency Figure 9. Charge Injection vs. Source Voltage 35 0 –10 30 TA = 25°C VDD = 5V, 3.3V S1A to S1B –20 tON (3.
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ADG854 0 –20 TA = 25°C VDD = 5V, 3.3V –60 –80 –100 –120 –140 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 07087-015 PSRR (dB) –40 Figure 15. PSRR vs. Frequency Rev.
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ADG854 TEST CIRCUITS S A IDS D ID (OFF) A VS VD V1 07087-020 IS (OFF) Figure 17. Off Leakage RON = V1/IDS S NC ID (ON) D A VD Figure 18. On Leakage Figure 16. On Resistance VDD 0.1µF VDD VS VOUT D RL 50Ω IN 50% VIN 50% CL 35pF 90% VOUT 90% GND tON tOFF 07087-022 S1B S1A Figure 19. Switching Times, tON, tOFF 0.1µF VDD VDD VIN S1B S1A VOUT VOUT D RL IN CL 35pF 50Ω 80% 50% 80% tBBM tBBM 07087-023 GND Figure 20.
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ADG854 VDD VDD 0.1µF 0.1µF NETWORK ANALYZER S1B S1A VS D GND VOUT VS D S1B RL 50Ω GND CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT VS Figure 24. Channel-to-Channel Crosstalk (S1A to S1B/S2A to S2B) VDD NETWORK ANALYZER NETWORK ANALYZER VOUT 50Ω S1A 50Ω VS GND VOUT 50Ω VS INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH D2 NC S2B D RL 50Ω S2A S1A D1 S1B CHANNEL-TO-CHANNEL CROSSTALK = 20 log NC 50Ω VOUT VS Figure 25.
PAGE 12
ADG854 TERMINOLOGY CD, CS (On) On switch capacitance. Measured with reference to ground. IDD Positive supply current. CIN Digital input capacitance. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. tON Delay time between the 50% and 90% points of the digital input and switch on condition. RFLAT (ON) The difference between the maximum and minimum values of on resistance as measured on the switch.
PAGE 13
ADG854 OUTLINE DIMENSIONS 0.20 DIA TYP 0.55 0.40 0.30 1.30 1 1.60 0.40 BSC 6 4 0.35 0.30 0.25 BOTTOM VIEW TOP VIEW 0.60 0.55 0.50 PIN 1 IDENTIFIER 9 0.05 MAX 0.02 NOM 033007-A 0.20 BSC SEATING PLANE Figure 26. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ] 1.30 × 1.
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ADG854 NOTES Rev.
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ADG854 NOTES Rev.