Datasheet

Data Sheet ADG738/ADG739
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V. All specifications −40°C to +105°C, unless otherwise noted.
Table 3.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments Min Max
f
SCLK
30 MHz SCLK cycle frequency
t
1
33 ns SCLK cycle time
t
2
13 ns SCLK high time
t
3
13 ns SCLK low time
t
4
0 ns
SYNC
to SCLK active edge setup time
t
5
5
ns
Data setup time
t
6
4.5 ns Data hold time
t
7
0 ns SCLK falling edge to
SYNC
rising edge
t
8
33 ns Minimum
SYNC
high time
t
9
3
20 ns min SCLK rising edge to DOUT valid
1
See Figure 3.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
C
L
= 20 pF, R
L
= 1 kΩ.
Figure 3. 3-Wire Serial Interface Timing Diagram
SCLK
SYNC
DIN
DB7
DB0
DB7
1
DB0
1
DOUT
1
DATA FROM LAST WRITE CYCLE.
t
3
t
2
t
1
t
4
t
8
t
6
t
5
t
9
t
7
10758-003