Datasheet

ManualsBrandsANALOG DEVICES ManualsInterface ICsInterface IC - multiplexers, demultiplexers TSSOP 16

CMOS, Low Voltage, 3-Wire

Serially-Controlled, Matrix Switches

Data Sheet

ADG738/ADG739

Rev. A Document Feedback

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FEATURES

3-wire serial interface

2.7 V to 5.5 V single supply

2.5 Ω on resistance

0.75 Ω on-resistance flatness

100 pA leakage currents

Single 8-to-1 multiplexer ADG738

Dual 4-to-1 multiplexer ADG739

Power-on reset

TTL/CMOS-compatible

Qualified for automotive applications

APPLICATIONS

Data acquisition systems

Communication systems

Relay replacement

Audio and video switching

GENERAL DESCRIPTION

The ADG738 and ADG739 are CMOS analog matrix switches

with a serially-controlled 3-wire interface. The ADG738 is an

8-channel matrix switch, while the ADG739 is a dual 4-channel

matrix switch. On resistance is closely matched between switches

and very flat over the full signal range.

FUNCTIONAL BLOCK DIAGRAMS

Figure 1.

Figure 2.

The ADG738 and ADG739 utilize a 3-wire serial interface

that is compatible with SPI™, QSPI™, MICROWIRE®, and some

DSP interface standards. The output of the input shift register,

DOUT, enables a number of these parts to be daisy-chained.

On power-up, the internal input shift register contains all zeros

and all switches are in the off state.

Each switch conducts equally well in both directions when on,

making these parts suitable for both multiplexing and demulti-

plexing applications. As each switch is turned on or off by a

separate bit, these parts can also be configured as a type of

switch array, where any, all, or none of the eight switches may

be closed at any time. The input signal range extends to the

supply rails.

All channels exhibit break-before-make switching action,

preventing momentary shorting when switching channels.

The ADG738 and ADG739 are available in 16-lead TSSOP

packages.

PRODUCT HIGHLIGHTS

1. 3-Wire Serial Interface.

2. Single Supply Operation. The ADG738/ADG739 are fully

specified and guaranteed with 3 V and 5 V supply rails.

3. Low On Resistance, 2.5 Ω typical.

4. Any configuration of switches may be on or off at any

one time.

5. Guaranteed Break-Before-Make Switching Action.

6. Small 16-lead TSSOP Package.

SCLK

DIN

SYNC

ADG738

RESET

DOUT

INPUT SHIFT

10758-001

S1A

SCLK

DIN

S4A

S1B

S4B

ADG739

DOUT

SYNC

INPUT SHIFT

10758-002

Summary of content (20 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAMS 3-wire serial interface 2.7 V to 5.5 V single supply 2.5 Ω on resistance 0.
PAGE 2
ADG738/ADG739 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Power-On Reset .......................................................................... 15 General Description ...............................................
PAGE 3
Data Sheet ADG738/ADG739 SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 25°C LEAKAGE CURRENTS Source Off Leakage IS (Off) Drain Off Leakage ID (Off) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 5 0.4 6 0.8 1 1.2 1.5 0.75 ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±0.3 ±0.6 ±1 ±1.3 ±1 ±1.3 2.4 0.8 0.005 ±0.
PAGE 4
ADG738/ADG739 Data Sheet VDD = 3 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 25°C Drain Off Leakage ID (Off) Channel On Leakage ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 12 0.4 16 1.2 1.4 3.5 ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±0.3 ±0.6 ±1 ±1.3 ±1 ±1.3 2.0 0.4 0.005 ±0.
PAGE 5
Data Sheet ADG738/ADG739 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V. All specifications −40°C to +105°C, unless otherwise noted. Table 3. Parameter 1, 2 fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 3 Min Limit at TMIN, TMAX Max 30 Unit MHz ns ns ns ns ns ns ns ns ns min 33 13 13 0 5 4.
PAGE 6
ADG738/ADG739 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 4. Parameter VDD to GND Analog, Digital Inputs1 Peak Current, S or D Continuous Current, Each S Continuous Current D ADG739 ADG738 Operating Temperature Range Industrial (B Version) Industrial (W Version) Storage Temperature Range Junction Temperature TSSOP Package θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering 1 Rating −0.3 V to +7 V −0.3 V to VDD + 0.
PAGE 7
Data Sheet ADG738/ADG739 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 16 SYNC SCLK 1 15 DOUT 14 GND DIN 3 S1 4 ADG738 TOP VIEW (Not to Scale) 13 VDD 12 S5 S2 5 S3 6 11 S6 S4 7 10 S7 D 8 9 S8 10758-004 RESET 2 Figure 4. ADG738 Pin Configuration Table 5. ADG738 Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 3 4, 5, 6, 7 8 9, 10, 11, 12 13 14 15 RESET DIN S1, S2, S3, S4 D S8, S7, S6, S5 VDD GND DOUT 16 SYNC Description Serial Clock Input.
PAGE 8
ADG738/ADG739 Data Sheet SCLK 1 16 DOUT 2 15 GND DIN 3 14 VDD ADG739 13 S1B TOP VIEW (Not to Scale) 12 S2B S3A 6 11 S3B S4A 7 10 DA 8 9 S1A 4 S2A 5 S4B DB 10758-005 SYNC Figure 5. ADG739 Pin Configuration Table 6. ADG739 Pin Function Descriptions Pin No. 1 Mnemonic SCLK 2 SYNC 3 DIN 4, 5, 6, 7 8, 9 10, 11, 12, 13 14 15 16 S1A, S2A, S3A, S4A DA, DB S4B, S3B, S2B, S1B VDD GND DOUT Description Serial Clock Input.
PAGE 9
Data Sheet ADG738/ADG739 TYPICAL PERFORMANCE CHARACTERISTICS 0.12 8 VDD = 5V VSS = 0V TA = 25°C TA = 25°C VSS = 0V 7 0.08 VDD = 2.7V ID (ON) VDD = 3.3V 5 4 VDD = 4.5V VDD = 5.5V 3 0.04 CURRENT (nA) ON RESISTANCE (Ω) 6 0 IS (OFF) –0.04 2 ID (OFF) –0.08 0 1 2 3 4 –0.12 10758-006 0 5 VD OR VS – DRAIN OR SOURCE VOLTAGE (V) 1 2 3 4 5 VD [VS] (V) Figure 6. On Resistance as a Function of VD (VS) 8 0 10758-009 1 Figure 9.
PAGE 10
ADG738/ADG739 Data Sheet 0.35 20 TA = 25°C VDD = 3V 0.30 10 VDD = 5V VSS = 0V 0 QINJ (pC) CURRENT (nA) 0.25 0.20 0.15 ID (ON) VDD = 3V VSS = 0V –10 –20 0.10 ID (OFF) IS (OFF) 0 20 40 60 100 80 120 TEMPERATURE (°C) –40 0 2 3 4 5 VOLTAGE (V) Figure 12. Leakage Currents as a Function of Temperature, VDD = 3 V 10m 1 10758-014 0 –30 10758-012 0.05 Figure 14. Charge Injection vs.
PAGE 11
Data Sheet ADG738/ADG739 0 0 VDD = 5V TA = 25°C ADG738 –20 ADG739 ATTENUATION (dB) ATTENUATION (dB) –5 –40 –60 –80 –10 –15 100k 1M 10M 100M FREQUENCY (Hz) Figure 16. Off Isolation vs. Frequency 0 VDD = 5V TA = 25°C –60 –80 –100 1M 10M FREQUENCY (Hz) 100M 10758-017 ATTENUATION (dB) –40 100k 1M 10M FREQUENCY (Hz) Figure 18. On Response vs. Frequency –20 –120 30k VDD = 5V TA = 25°C –20 100k 30k Figure 17. Crosstalk vs. Frequency Rev.
PAGE 12
ADG738/ADG739 Data Sheet TEST CIRCUITS S1 NC D ID (ON) A S2 V Sn D IDS VS VD 10758-025 RON = V/IDS Figure 19. On Resistance IS (OFF) A A S1 D NC = NO CONNECT VD 10758-028 S Figure 21. IS, ID (On) ID (OFF) A Sn VD 10758-026 VS Figure 20. ID (Off), IS (Off) VDD VDD SYNC ADG738* S1 SYNC 50% 50% VS1 S2 THRU S7 VS1 VS8 GND CL 35pF RL 300Ω VOUT 90% VS1 = VS8 VOUT 80% 80% VOUT 90% tOFF *SIMILAR CONNECTION FOR ADG739. tOPEN tON Figure 22.
PAGE 13
Data Sheet ADG738/ADG739 VDD VDD VDD S1 S8 VS ADG738* VDD ADG738* 50Ω D S1 D RL 50Ω S2 VS VOUT GND RL 50Ω VOUT S8 GND *SIMILAR CONNECTION FOR ADG739. S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS AND ON FOR BANDWIDTH MEASUREMENTS INSERTION LOSS = 20LOG10 Figure 24. Channel-to-Channel Crosstalk VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 25. Off Isolation and Bandwidth Rev.
PAGE 14
ADG738/ADG739 Data Sheet TERMINOLOGY CS (Off) Off switch source capacitance. Measured with reference to ground. VDD Most positive power supply potential. IDD Positive supply current. CD (Off) Off switch drain capacitance. Measured with reference to ground. GND Ground (0 V) reference. CD, CS (On) On switch capacitance. Measured with reference to ground. S Source terminal. May be an input or output. CIN Digital input capacitance. D Drain terminal. May be an input or output.
PAGE 15
Data Sheet ADG738/ADG739 THEORY OF OPERATION POWER-ON RESET During device power-up, all switches will be in the off condition and the internal input shift register is filled with zeros and remains so until a valid write takes place. SERIAL INTERFACE S8 S7 S6 S5 S4 S3 S2 S1 DATA BITS Figure 26.
PAGE 16
ADG738/ADG739 Data Sheet 8051 INTERFACE TO ADG738/ADG739 MC68HC11 INTERFACE TO ADG738/ADG739 A serial interface between the ADG738/ADG739 and the 8051 is shown in Figure 28. TXD of the 8051 drives SCLK of the ADG738/ADG739, while RXD drives the serial data line, DIN. P3.3 is a bit-programmable pin on the serial port and is used to drive SYNC. Figure 29 shows an example of a serial interface between the ADG738/ADG739 and the MC68HC11 microcontroller.
PAGE 17
Data Sheet ADG738/ADG739 APPLICATIONS INFORMATION EXPAND THE NUMBER OF SELECTABLE SERIAL DEVICES USING AN ADG739 ADG739 SYNC DIN The dual 4-channel ADG739 multiplexer can be used to multiplex a single chip select line to provide chip selects for up to four devices on the SPI bus. Figure 30 illustrates the ADG739 in such a typical configuration. All devices receive the same serial clock and serial data, but only one device receives the SYNC signal at any one time.
PAGE 18
ADG738/ADG739 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 32.
PAGE 19
Data Sheet ADG738/ADG739 NOTES Rev.