Datasheet

REV. A
ADG725/ADG731
–5–
TIMING CHARACTERISTICS
1, 2
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCLK
30 MHz max SCLK Cycle Frequency
t
1
33 ns min SCLK Cycle Time
t
2
13 ns min SCLK High Time
t
3
13 ns min SCLK Low Time
t
4
13 ns min SYNC to SCLK Falling Edge Setup Time
t
5
40 ns min Minimum SYNC Low Time
t
6
5 ns min Data Setup Time
t
7
4.5 ns min Data Hold Time
t
8
33 ns min Minimum SYNC High Time
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DB7
DB0
t
8
t
4
t
5
t
6
t
7
t
2
t
3
t
1
Figure 1. 3-Wire Serial Interface Timing Diagram
A3 A2 A1 A0
EN
CSA
X
DB0 (LSB)
DB7 (MSB)
DATA BITS
CSB
Figure 2. ADG725 Input Shift Register Contents
A3 A2 A1 A0
EN CS
X
DB0 (LSB)
DB7 (MSB)
DATA BITS
A4
Figure 3. ADG731 Input Shift Register Contents