Datasheet

REV. A

ADG725/ADG731

–15–

SYNC signal at any one time. The mux addressed will be deter-

mined by the decoder. There will be some digital feedthrough

from the digital input lines. Using a burst clock will minimize the

effects of digital feedthrough on the analog signal channels.

Figure 9 shows a typical circuit.

ENABLE

DIN

SCLK

DGND

CODED

ADDRESS

DECODER

VDD

DIN

SCLK

DIN

SCLK

DIN

SCLK

ADG725/

ADG731

SYNC

DIN

SCLK

SYNC

OTHER SPI

DEVICE

ADG725/

ADG731

OTHER SPI

DEVICE

Figure 9. Addressing Multiple ADG725/ADG731s

Using a Decoder