Datasheet

ADG728/ADG729
–4– REV. C
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V. All specifications −40°C to +85°C, unless otherwise noted. See Figure 1.
Parameter Limit at T
MIN
, T
MAX
Unit Test Conditions/Comments
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 µs min SCL cycle time
t
2
0.6 µs min SCL high time, t
HIGH
t
3
1.3
µs min
SCL low time, t
LOW
t
4
0.6
µs min
Start/repeated start condition hold time, t
HD, STA
t
5
100 ns min Data setup time, t
SU, DAT
t
6
1
0.9 µs max Data hold time, t
HD, D AT
0 µs min
t
7
0.6 µs min Setup time for repeated start, t
SU, STA
t
8
0.6 µs min Stop condition setup time, t
SU, STO
t
9
1.3 µs min Bus free time between a stop condition and a start condition, t
BUF
t
10
300 ns max Rise time of both SCL and SDA when receiving, t
R
20 + 0.1C
b
2
ns min
t
11
250 ns max Fall time of SDA when receiving, t
F
300 ns max Fall time of SDA when transmitting, t
F
0.1C
b
2
ns min
C
b
2
400 pF max Capacitive load for each bus line
t
SP
3
50 ns max Pulse width of spike suppressed
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
2
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
3
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
t
3
t
2
t
1
t
4
t
8
t
6
t
5
t
9
t
7
t
4
t
11
t
10
SDA
SCL
START
CONDITION
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
01002-002
Figure 1. 2-Wire Serial Interface Timing Diagram