Datasheet

REV. 0
–5–
ADG726/ADG732
TIMING CHARACTERISTICS
1, 2, 3
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
t
1
0 ns min CS to WR Setup Time
t
2
0 ns min CS to WR Hold Time
t
3
10 ns min WR Pulsewidth
t
4
10 ns min Time between WR Cycles
t
5
5 ns min Address, Enable Setup Time
t
6
2 ns min Address, Enable Hold Time
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
).
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
t
1
t
2
t
3
t
4
t
5
t
6
CS
WR
A0, A1, A2, A3, (A4)
EN
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to changing the address and enable the inputs.
Input data is latched on the rising edge of WR. The ADG726
has two CS inputs. This enables the part to be used either as a
dual 16-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie CSA and
CSB together.