Datasheet

ADG714/ADG715 Data Sheet
Rev. E | Page 8 of 21
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
C
b
400 pF max Capacitive load for each bus line
t
SP
3
50 ns max Pulse width of spike suppressed
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
2
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 × V
DD
and 0.7 × V
DD
.
3
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Timing Diagrams
SCLK
SYNC
DIN
DOUT
t
1
t
2
t
4
t
6
t
5
t
9
t
8
t
3
t
7
t
11
DB0DB7
DB7*
DB6* DB2* DB1* DB0*
t
10
*DATA FROM PREVIOUS WRITE CYCLE
00043-003
Figure 3. 3-Wire Serial Interface Timing Diagram
SDA
SCL
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
8
t
1
t
7
t
4
t
5
t
11
t
2
t
6
t
10
t
3
t
4
t
9
00043-004
Figure 4. 2-Wire Serial Interface Timing Diagram
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