Datasheet

Data Sheet ADG714/ADG715
Rev. E | Page 21 of 21
OUTLINE DIMENSIONS
24
13
121
6.40 BSC
4.50
4.40
4.30
PIN 1
7.90
7.80
7.70
0.15
0.05
0.30
0.19
0.65
BSC
1.20
MAX
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 30. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
0.30
0.25
0.20
0.80
0.75
0.70
0.20 MIN
2.20
2.10 SQ
2.00
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO JEDEC STANDARDS MO-220-WGGD-8.
BOTTOM VIEW
TOP VIEW
SIDE VIEW
4.10
4.00 SQ
3.90
0.05 MAX
0.02 NOM
0.203 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
7
12
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-19-2017-B
EXPOSED
PAD
PKG-004714
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 31. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
ADG714BRUZ −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADG714BRUZ-REEL −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADG714BRUZ-REEL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADG714BCPZ-REEL7 −40°C to +85°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-10
ADG715BRUZ −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADG715BRUZ-REEL −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
ADG715BRUZ-REEL7 −40°C to +85°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24
1
Z = RoHS Compliant Part.
I
2
C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
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D00043-0-6/18(E)
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