Datasheet

ADG714/ADG715 Data Sheet
Rev. E | Page 18 of 21
Input Shift Register
The input shift register is eight bits wide. Figure 24 illustrates
the contents of the input shift register. Data is loaded into the
device as an 8-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 4.
The 8-bit word consists of eight data bits, each controlling one
switch. MSB (Bit 7) is loaded first.
Write Operation
When writing to the ADG715, the user begins with an address
byte and an R/
W
bit, after which the switch acknowledges that
it is prepared to receive data by pulling SDA low. This address
byte is followed by the 8-bit word. The write operation for the
switch is shown in Figure 25.
Read Operation
When reading data back from the ADG715, the user begins
with an address byte and an R/
W
bit, after which the switch
acknowledges that it is prepared to transmit data by pulling
SDA low. The readback operation is a single byte that consists of
the eight data bits in the input register. The read operation for
the switch is shown in Figure 26.
SCL
SDA
S8
S7
S6
S5 S4 S3 S2 S1
A0
R/W
ACK
BY
ADG715
ACK
BY
ADG715
START
COND
BY
MASTER
STOP
COND
BY
MASTER
ADDRESS BYTE
DATA BYTE
A1
1 10 0 0
00043-024
Figure 25. ADG715 Write Sequence
SCL
SDA
S8 S7 S6 S5 S4 S3 S2 S1A0 R/W
ACK
BY
ADG715
NO ACK
BY
MASTER
START
COND
BY
MASTER
STOP
COND
BY
MASTER
ADDRESS BYTE DATA BYTE
A1
1 10 0 0
00043-025
Figure 26. ADG715 Readback Sequence
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