Datasheet

Data Sheet ADG714/ADG715
Rev. E | Page 17 of 21
THEORY OF OPERATION
The ADG714 and ADG715 are serially controlled, octal SPST
switches, controlled by either a 2- or 3-wire interface. Each bit
of the 8-bit serial word corresponds to one switch of the device.
A Logic 1 in the bit position turns the switch on, and a Logic 0
turns the switch off. Each switch is independently controlled by
an individual bit, which provides the option of having any, all,
or none of the switches on.
When changing the switch conditions, a new 8-bit word is
written to the input shift register. Some of the bits may be the
same as the previous write cycle because the user may not
change the state of some switches. To minimize glitches on the
output of these switches, the devices compare the state of
switches from the previous write cycle. When the switches are
already in the on condition and are required to stay on, there
are minimal glitches on the output of the switch.
POWER-ON RESET
On power-up of the device, all switches are in the off condition,
the internal shift register is filled with zeros, and the register
remains so until a valid write takes place.
SERIAL INTERFACE
3-Wire Serial Interface
The ADG714 has a 3-wire serial interface (
SYNC
, SCLK, and
DIN), that is compatible with SPI, QSPI, MICROWIRE interface
standards, and most DSP interface standards. Figure 3 shows
the timing diagram of a typical write sequence.
Data is written to the 8-bit shift register via DIN under the
control of the
SYNC
and SCLK signals. Data may be written to
the shift register in more or less than eight bits. In each case, the
shift register retains the last eight written bits.
When
SYNC
goes low, the input shift register is enabled. Data
from DIN is clocked into the shift register on the falling edge of
SCLK. Each bit of the 8-bit word corresponds to one of the eight
switches. Figure 24 shows the contents of the input shift register.
Data appears on the DOUT pin on the rising edge of SCLK
suitable for daisy chaining, delayed by eight bits. When all eight
bits have been written into the shift register, the
SYNC
line is
brought high again. The switches are updated with the new
configuration, and the input shift register is disabled. With
SYNC
held high, the input shift register is disabled so that
further data or noise on the DIN line has no effect on the shift
register.
S8 S7 S6 S5 S4 S3 S2 S1
DB7 (MSB) DB0 (LSB)
DATA BITS
00043-023
Figure 24. Input Shift Register Contents
2-Wire Serial Interface
The ADG715 is controlled via an I
2
C-compatible serial bus.
This device is connected to the bus as a slave device (no clock is
generated by the switch).
The ADG715 has a 7-bit slave address. The five MSBs are 10010
and the two LSBs are determined by the state of the A0 and A1 pins.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is when a high to low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of a 7-bit slave address
followed by an R/
W
bit (this bit determines whether data is
read from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (the pulling of SDA line is termed the
acknowledge bit). At this stage, all other devices on the bus
remain idle while the selected device waits for data to be
written to or read from its serial register. If the R/
W
bit is
high, the master reads from the slave device. If the R/
W
bit
is low, the master writes to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
3. When all data bits are read or written, a stop condition is
established by the master. A stop condition is defined as a
low to high transition on the SDA line while SCL is high.
In write mode, the master pulls the SDA line high during
the tenth clock pulse to establish a stop condition. In read
mode, the master issues a no acknowledge for the ninth
clock pulse, and the SDA line remains high. The master
brings the SDA line low before the tenth clock pulse and
then high during the tenth clock pulse to establish a stop
condition.
See Figure 25 for an ADG715 write sequence.
A repeated write function gives the user the flexibility to update
the matrix switch a number of times after addressing the device
only once. During the write cycle, each data byte updates the
configuration of the switches. For example, after the matrix
switch acknowledges its address byte and receives one data byte,
the switches update after the data byte. If another data byte is
written to the matrix switch while still in the same addressed
slave device, this data byte also causes a switch configuration
update. Repeating the read of the matrix switch is also allowed.
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