Datasheet

ADG714/ADG715 Data Sheet
Rev. E | Page 12 of 21
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2
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20
21
22
23
24
19
18
17
16
15
14
1312
11
ADG715
(Not to Scale)
TOP VIEW
A0
RESET
A1
V
SS
S8
D8
S7
D7
S6
D6
S5
D5
SCL
V
DD
SDA
GND
S1
D1
S2
D2
S3
D3
S4
D4
00043-007
Figure 7. ADG715 Pin Configuration
Table 10. ADG715 Pin Function Descriptions
Pin No. Mnemonic Description
1 SCL
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into the 8-bit input
shift register. Clock rates of up to 400 kbps are accommodated with this 2-wire serial interface.
2 V
DD
Positive Analog Supply Voltage.
3
SDA
Serial Data Line. This pin is used in conjunction with the SCL line to clock data into the 8-bit input
shift register during the write cycle and used to read back one byte of data during the read cycle.
SDA is a bidirectional open-drain data line that is pulled to the supply with an external pull-up
resistor.
4 GND Ground Reference.
5, 7, 9, 11, 14, 16, 18, 20 Sx Source. These pins may be an input or an output.
6, 8, 10, 12, 13, 15, 17, 19 Dx Drain. These pins may be an input or an output.
21 V
SS
Negative Analog Supply Voltage. For single-supply operation, tie this pin to ground.
22 A1 Address Input. This pin sets the second LSB of the 7-bit slave address.
23
RESET Active Low Control Input. This pin clears the input register and turns all switches to the off
condition.
24 A0 Address Input. This pin sets the LSB of the 7-bit slave address.
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