Datasheet
Data Sheet ADG714/ADG715
Rev. E | Page 11 of 21
GND
S1
D1
S2
D2
S3
S7
D8
S8
V
SS
D7
S6
D3
S4
D4
S5
D6
D5
SYNC
SCLK
V
DD
DIN
RESET
DOUT
2
1
3
4
5
6
18
17
16
15
14
13
8
9
10
1
1
7
12
20
19
21
22
23
24
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
ADG714
TO
P
VIEW
(Not to Scale)
00043-006
Figure 6. ADG714 LFCSP Pin Configuration
Table 9. ADG714 Pin Function Descriptions
Pin No. Mnemonic Description
1
GND
Ground (0 V) Reference.
2, 4, 6, 8, 11, 13, 15, 17 Sx Source. These pins may be an input or an output.
3, 5, 7, 9, 10, 12, 14, 16 Dx Drain. These pins may be an input or an output.
18 V
SS
Most Negative Power Supply Potential. In single-supply applications, V
SS
is
connected to ground.
19
DOUT
Serial Data Output. This pin is used for daisy-chaining a number of these devices
together or for reading back data in the shift register for diagnostic purposes. The
serial data is transferred on the rising edge of SCLK and is valid on the falling edge
of the clock. Pull this open-drain output to the supply with an external resistor.
20
RESET RESET. Under normal operation, drive the RESET pin with a 2.7 V to 5 V supply. Pull
the pin low (<0.8 V) for a short period (15 ns is sufficient) to complete a hardware
reset. All switches are opened and the appropriate registers are cleared to 0.
When using the
RESET pin to complete a hardware reset, all other SPI pins (SYNC,
SCLK, and DIN) must be driven low.
21
SYNC Active Low Control Input. This pin is the frame synchronization signal for the input
data. When
SYNC goes low, this pin powers on the SCLK and DIN buffers and
enables the input shift register. Data is transferred in on the falling edges of the
following clock cycle. Taking
SYNC high updates the switch condition.
22 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge
of the serial clock input. Data is transferred at rates of up to 50 MHz.
23 V
DD
Most Positive Power Supply Potential.
24
DIN
Serial Data Input. This device has an 8-bit shift register. Data is clocked into the
register on the falling edge of the serial clock input.
EP EP Exposed Pad. Exposed pad tied to the substrate, V
SS
.
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