Datasheet
ADG714/ADG715 Data Sheet
Rev. E | Page 10 of 21
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
19
18
17
16
15
14
13
12
11
ADG714
(Not to Scale)
TOP VIEW
RESET
DOUT
V
SS
S8
D8
S7
D7
S6
D6
S5
D5
SCLK
V
DD
DIN
GND
S1
D1
S2
D2
S3
D3
S4
D4
SYNC
00043-005
Figure 5. ADG714 TSSOP Pin Configuration
Table 8. ADG714 Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. These devices accommodate serial input rates of up to 30 MHz.
2 V
DD
Positive Analog Supply Voltage.
3 DIN
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial
clock input.
4 GND Ground Reference.
5, 7, 9, 11, 14, 16, 18, 20 Sx Source. These pins may be an input or an output.
6, 8, 10, 12, 13, 15, 17, 19 Dx Drain. These pins may be an input or an output.
21 V
SS
Negative Analog Supply Voltage. For single-supply operation, tie this pin to ground.
22 DOUT
Serial Data Output. This pin allows a number of devices to be daisy-chained. Data is clocked out
of the input shift register on the rising edge of SCLK. DOUT is an open-drain output that is pulled
to the supply with an external pull-up resistor.
23
RESET Active Low Control Input. This pin clears the input register and turns all switches to the off
condition.
24
SYNC Active Low Control Input. This pin is the frame synchronization signal for the input data. When
SYNC goes low, this pin powers on the SCLK and DIN buffers and the input shift register is
enabled. Data is transferred on the falling edges of the following clock cycle. Taking SYNC high
updates the switches.
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