Datasheet

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CMOS, Low Voltage

Serially Controlled, Octal SPST Switches

Data Sheet

ADG714/ADG715

Rev. E Document Feedback

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FEATURES

SPI/QSPI/MICROWIRE-compatible interface (ADG714)

ADG715: I

C-compatible interface (ADG715)

2.7 V to 5.5 V single supply

±2.5 V dual supply

2.5 Ω on resistance

0.6 Ω on resistance flatness

0.1 nA leakage currents

Octal SPST

Power-on reset

Fast switching times

TTL/CMOS compatible

24-lead TSSOP and 24-lead LFCSP

APPLICATIONS

Data acquisition systems

Communication systems

Relay replacement

Audio and video switching

GENERAL DESCRIPTION

The ADG714/ADG715 are complementary metal-oxide

semiconductor (CMOS), octal single-pole, single-throw (SPST)

switches, controlled via either a 2- or 3-wire serial interface. On

resistance is closely matched between the switches and is flat

over the full signal range. Each switch conducts equally well in

both directions, and the input signal range extends to the

supplies. Data is written to these devices in the form of 8 bits,

each bit corresponding to one channel.

The ADG714 uses a 3-wire serial interface that is compatible

with serial peripheral interface (SPI), QSPI™, MICROWIRE™

interface standards, and most digital signal processing (DSP)

interface standards. The output of the shift register DOUT

enables a number of these devices to be daisy-chained.

The ADG715 uses a 2-wire serial interface that is compatible

with the I

C interface standard. The ADG715 has four hardwired

addresses, selectable from two external address pins (A0 and A1).

The pins allow the two LSBs of the 7-bit slave address to be set

by the user. A maximum of four of these devices may be

connected to the bus.

On power-up of these devices, all switches are in the off

condition, and the internal registers contain all zeros.

A low power consumption and operating supply range of 2.7 V

to 5.5 V make these devices ideal for many applications. These

devices can also be supplied from a dual ±2.5 V supply. The

ADG714 is available in a 24-lead TSSOP and a 24-lead LFCSP,

FUNCTIONAL BLOCK DIAGRAMS

ADG714

DOUT

INPUT SHIFT

SCLK DIN SYNC RESET

00043-001

Figure 1. ADG714 Functional Block Diagram

ADG715

INTERFACE

LOGIC

SDA SCL

A0 A1

RESET

00043-002

Figure 2. ADG715 Functional Block Diagram

and the ADG715 is available in a 24-lead TSSOP.

PRODUCT HIGHLIGHTS

1. 2- or 3-wire serial interface.

2. Single-/dual-supply operation.

The ADG714 and ADG715 are fully speciﬁed and

guaranteed with 3 V, 5 V, and ±2.5 V supply rails.

3. Low on resistance, typically 2.5 Ω.

4. Low leakage.

5. Power-on reset.

6. A 24-lead TSSOP for both the ADG714 and the ADG715.

A 24-lead LFCSP for the ADG714.

Downloaded from Arrow.com.

Summary of content (21 pages)

PAGE 1
FEATURES FUNCTIONAL BLOCK DIAGRAMS SPI/QSPI/MICROWIRE-compatible interface (ADG714) ADG715: I2C-compatible interface (ADG715) 2.7 V to 5.5 V single supply ±2.5 V dual supply 2.5 Ω on resistance 0.6 Ω on resistance flatness 0.1 nA leakage currents Octal SPST Power-on reset Fast switching times TTL/CMOS compatible 24-lead TSSOP and 24-lead LFCSP ADG714 S1 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8 D8 INPUT SHIFT REGISTER 00043-001 DOUT SCLK DIN SYNC RESET APPLICATIONS Figure 1.
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ADG714/ADG715 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ......................... 10 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 13 General Description .........................................................................
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Data Sheet ADG714/ADG715 SPECIFICATIONS 5 V SINGLE SUPPLY VDD = 5 V ± 10%, VSS = 0 V, and GND = 0 V, unless otherwise noted. Temperature range is −40°C to +85°C. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON +25°C 2.5 4.5 On Resistance Match Between Channels, ΔRON On Resistance Flatness, RFLAT(ON) −40°C to +85°C Unit 0 V to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 5 0.4 0.8 0.6 1.
PAGE 4
ADG714/ADG715 Data Sheet Parameter Off Time, tOFF ADG714 +25°C −40°C to +85°C 8 15 ADG715 85 130 Break-Before-Make Time Delay, tD 8 1 Charge Injection, QINJ Off Isolation ±3 −60 −80 −70 −90 155 −0.
PAGE 5
Data Sheet Parameter DIGITAL INPUTS, SCL, SDA Input Voltage High, VINH ADG714/ADG715 +25°C Low, VINL Input Leakage Current, IIN −40°C to +85°C Unit 0.7 × VDD VDD + 0.3 −0.3 0.3 × VDD V min V max V min V max µA typ µA max V min pF typ 0.005 ±1 Input Hysteresis, VHYST Input Capacitance, CIN LOGIC OUTPUT, (SDA) Output Voltage Low, VOL DYNAMIC CHARACTERISTICS On Time, tON ADG714 0.05 × VDD 6 0.4 0.
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ADG714/ADG715 Parameter LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID (ON), IS (ON) DIGITAL INPUTS Input Voltage High, VINH Low, VINL High or Low Input Current, IINH or IINL Data Sheet +25°C −40°C to +85°C ±0.01 ±0.1 ±0.01 ±0.1 ±0.01 ±0.1 ±0.3 ±0.3 ±0.3 1.7 0.7 0.005 ±0.
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Data Sheet ADG714/ADG715 Parameter Off Switch Source Capacitance, CS (OFF) Off Switch Drain Capacitance, CD (OFF) On Switch Capacitance, C D (ON), C S (ON) POWER REQUIREMENTS Positive Power Supply Current, IDD +25°C 11 11 22 −40°C to +85°C 15 µA typ µA max µA typ µA max 25 Negative Power Supply Current, ISS Unit pF typ pF typ pF typ 15 25 Test Conditions/Comments VDD = +2.75 V, VSS = −2.75 V Digital inputs = 0 V or VDD TIMING CHARACTERISTICS ADG714 VDD = 2.7 V to 5.5 V.
PAGE 8
ADG714/ADG715 Parameter Cb tSP3 Data Sheet Limit at TMIN, TMAX 400 50 Unit pF max ns max Conditions/Comments Capacitive load for each bus line Pulse width of spike suppressed A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 × VDD and 0.7 × VDD.
PAGE 9
Data Sheet ADG714/ADG715 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 6. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Continuous Current, Sx or Dx Operating Temperature Range Storage Temperature Range Junction Temperature Lead Temperature, Soldering (10 sec) Infrared Reflow (20 sec) 1 Rating 7V −0.
PAGE 10
ADG714/ADG715 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCLK 1 24 SYNC VDD 2 23 RESET DIN 3 22 DOUT GND 4 21 VSS 5 6 ADG714 20 S8 TOP VIEW 19 D8 (Not to Scale) S2 7 18 S7 D2 8 17 D7 S3 9 16 S6 D3 10 15 D6 S4 11 14 S5 D4 12 13 D5 00043-005 S1 D1 Figure 5. ADG714 TSSOP Pin Configuration Table 8. ADG714 Pin Function Descriptions Pin No.
PAGE 11
19 DOUT 21 SYNC 20 RESET 22 SCLK 24 DIN ADG714/ADG715 23 VDD Data Sheet 18 VSS GND 1 S1 2 17 S8 D1 3 ADG714 16 D8 S2 4 TOP VIEW (Not to Scale) 15 S7 D2 5 14 D7 S3 6 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 00043-006 D6 12 S5 11 D5 10 D4 9 S4 8 D3 7 13 S6 Figure 6. ADG714 LFCSP Pin Configuration Table 9. ADG714 Pin Function Descriptions Pin No.
PAGE 12
ADG714/ADG715 Data Sheet SCL 1 24 A0 VDD 2 23 RESET SDA 3 22 A1 GND 4 21 VSS S1 5 D1 6 ADG715 S8 TOP VIEW 19 D8 (Not to Scale) S2 7 18 S7 D2 8 17 D7 S3 9 16 S6 D3 10 15 D6 S4 11 14 S5 D4 12 13 D5 00043-007 20 Figure 7. ADG715 Pin Configuration Table 10. ADG715 Pin Function Descriptions Pin No. 1 Mnemonic SCL 2 3 VDD SDA 4 5, 7, 9, 11, 14, 16, 18, 20 6, 8, 10, 12, 13, 15, 17, 19 21 22 23 GND Sx Dx VSS A1 RESET 24 A0 Description Serial Clock Line.
PAGE 13
Data Sheet ADG714/ADG715 TYPICAL PERFORMANCE CHARACTERISTICS 8 8 TA = 25°C VSS = GND 7 6 6 ON RESISTANCE (Ω) VDD = 2.7V 5 VDD = 3.3V 4 VDD = 4.5V VDD = 5.5V 4 –40°C 3 2 2 1 1 0 1 2 3 4 VD, VS, DRAIN OR SOURCE VOLTAGE (V) 0 00043-008 0 5 +25°C 0 0.5 1.5 1.0 2.0 Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, VDD = 3 V 8 8 TA = 25°C 7 7 6 6 ON RESISTANCE (Ω) ON RESISTANCE (Ω) 3.0 2.5 VD OR VS DRAIN OR SOURCE VOLTAGE (V) Figure 8.
PAGE 14
ADG714/ADG715 Data Sheet 0.04 0.10 VDD = 3V VSS = GND VD = 3V/1V VS = 1V/3CV VDD = 3V VSS = GND TA = 25°C 0.05 IS, ID (ON) 0 IS (OFF) ID (OFF) IS, ID (ON) CURRENT (nA) –0.02 0 ID (OFF) IS (OFF) –0.05 0 0.5 1.0 1.5 2.5 2.0 3.0 VOLTAGE (V) –0.10 00043-014 –0.04 10 20 30 40 50 70 60 80 TEMPERATURE (°C) Figure 14. Leakage Currents as a Function of VD (VS), Single Supply 00043-017 CURRENT (nA) 0.02 Figure 17.
PAGE 15
Data Sheet ADG714/ADG715 45 –40 VSS = GND VDD = 5V TA = 25°C 40 tON, VDD = 3V –50 35 30 TIME (ns) CROSSTALK (dB) –60 –70 tON, VDD = 5V 25 20 tOFF, VDD = 3V 15 –80 10 –90 tOFF, VDD = 5V 5 100k 1M 10M 100M FREQUENCY (Hz) 0 10 30 40 50 70 60 80 TEMPERATURE (°C) Figure 22. tON/tOFF Times vs. Temperature for the ADG714 Figure 20. Crosstalk vs. Frequency 0 10 TA = 25°C –10 VDD = +3.
PAGE 16
ADG714/ADG715 Data Sheet TERMINOLOGY VDD Most positive power supply potential. CD (OFF) Off switch drain capacitance. CD (OFF) is measured with reference to ground. VSS Most negative power supply in a dual-supply application. In single-supply applications, tie this pin to ground. CD (ON), CS (ON) On switch capacitance. CD (ON), CS (ON) is measured with reference to ground. IDD Positive supply current. CIN Digital input capacitance. ISS Negative supply current.
PAGE 17
Data Sheet ADG714/ADG715 THEORY OF OPERATION The ADG714 and ADG715 are serially controlled, octal SPST switches, controlled by either a 2- or 3-wire interface. Each bit of the 8-bit serial word corresponds to one switch of the device. A Logic 1 in the bit position turns the switch on, and a Logic 0 turns the switch off. Each switch is independently controlled by an individual bit, which provides the option of having any, all, or none of the switches on.
PAGE 18
ADG714/ADG715 Data Sheet Input Shift Register byte is followed by the 8-bit word. The write operation for the switch is shown in Figure 25. The input shift register is eight bits wide. Figure 24 illustrates the contents of the input shift register. Data is loaded into the device as an 8-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 4. The 8-bit word consists of eight data bits, each controlling one switch. MSB (Bit 7) is loaded ﬁrst.
PAGE 19
Data Sheet ADG714/ADG715 APPLICATIONS INFORMATION MULTIPLE DEVICES ON ONE BUS complete, SYNC is brought high, and all switches are updated simultaneously. Further shift registers may be added in a series. Figure 27 shows four ADG715 devices on the same serial bus. Each has a different slave address because the state of the A0 and A1 pins is different. This difference allows each switch to be written to or read from independently.
PAGE 20
ADG714/ADG715 Data Sheet DECODING MULTIPLE ADG714 DEVICES USING THE ADG739 VDD R SYNC DIN SCLK VDD R VDD DIN 1/2 OF ADG739 S1A SYNC1 DA SCLK VDD S2A R S3A DIN SCLK DIN SYNC FROM MICROCONTROLLER OR DSP OTHER SPI DEVICE SYNC S4A Rev. E | Page 20 of 21 Downloaded from Arrow.com. ADG714 SYNC SCLK VDD SYNC2 R OTHER SPI DEVICE SYNC DIN SCLK DIN SCLK Figure 29.
PAGE 21
Data Sheet ADG714/ADG715 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.75 0.60 0.45 8° 0° 0.20 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 30. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters DETAIL A (JEDEC 95) 4.10 4.00 SQ 3.90 1 0.50 BSC 2.20 2.10 SQ 2.00 EXPOSED PAD 13 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004714 SEATING PLANE 0.