Datasheet

ADG714/ADG715
–6–
REV.
ADG715 TIMING CHARACTERISTICS
1
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCL
400 kHz max SCL Clock Frequency
t
1
2.5 μs min SCL Cycle Time
t
2
0.6 μs min t
HIGH
, SCL High Time
t
3
1.3 μs min t
LOW
, SCL Low Time
t
4
0.6 μs min t
HD, STA
, Start/Repeated Start Condition Hold Time
t
5
100 ns min t
SU, DAT
, Data Setup Time
t
6
2
0.9 μs max t
HD, DAT
, Data Hold Time
0 μs min
t
7
0.6 μs min t
SU, STA
, Setup Time for Repeated Start
t
8
0.6 μs min t
SU, STO
, Stop Condition Setup Time
t
9
1.3 μs min t
BUF
, Bus Free Time Between a STOP Condition and
a Start Condition
t
10
300 ns max t
R
, Rise Time of Both SCL and SDA When Receiving
20 + 0.1C
b
3
ns min
t
11
250 ns max t
F
, Fall Time of SDA When Receiving
t
11
300 ns max t
F
, Fall Time of SDA When Transmitting
0.1C
b
3
ns min
C
b
400 pF max Capacitive Load for Each Bus Line
t
SP
4
50 ns max Pulsewidth of Spike Suppressed
NOTES
1
See Figure 2.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
4
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice.
SDA
SCL
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
8
t
1
t
7
t
4
t
5
t
11
t
2
t
6
t
10
t
3
t
4
t
9
Figure 2. 2-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)
C