Datasheet

ADG714/ADG715
–5–
REV.
ADG714 TIMING CHARACTERISTICS
1, 2
Parameter Limit at T
MIN
, T
MAX
Unit Conditions/Comments
f
SCLK
30 MHz max SCLK Cycle Frequency
t
1
33 ns min SCLK Cycle Time
t
2
13 ns min SCLK High Time
t
3
13 ns min SCLK Low Time
t
4
0 ns min SYNC to SCLK Rising Edge Setup Time
t
5
5 ns min Data Setup Time
t
6
4.5 ns min Data Hold Time
t
7
0 ns min SCLK Falling Edge to SYNC Rising Edge
t
8
33 ns min Minimum SYNC High Time
t
9
3
20 ns max SCLK Rising Edge to DOUT Valid
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
C
L
= 20 pF, R
L
= 1 kΩ.
Specifications subject to change without notice.
SCLK
SYNC
DIN
DOUT
t
8
t
4
t
6
t
5
t
2
t
3
t
1
t
7
t
9
DB0DB7
DB7
*
DB6
*
DB2
*
DB1
*
DB0
*
*
DATA FROM PREVIOUS WRITE CYCLE
Figure 1. 3-Wire Serial Interface Timing Diagram
(V
DD
= 2.7 V to 5.5 V. All specifications –40C to +85C unless otherwise noted.)
C