Datasheet

ADG714/ADG715
–15–
REV.
devices on the SPI bus. Figure 8 illustrates the ADG739 and mul-
tiple ADG714s in such a typical configuration. All devices receive
the same serial clock and serial data, but only one device will
receive the SYNC signal at any one time. The ADG739 is a serially
controlled device also. One bit programmable pin of the micro-
controller is used to enable the ADG739 via SYNC2, while
another bit programmable pin is used as the chip select for the
other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By bringing
SYNC1 low, the selected serial device hanging from the SPI bus
will be enabled and data will be clocked into its shift register on
the falling edges of SCLK. The convenient design of the matrix
switch allows for different combinations of the four serial
devices to be addressed at any one time. If more devices need
to be addressed via one chip select line, the ADG738 is an 8-
channel device and would allow further expansion of the chip
select scheme. There may be some digital feedthrough from the
digital input lines because SCLK and DIN are permanently
connected to each device. Using a burst clock will minimize the
effects of digital feedthrough on the analog channels.
OTHER
SPI
DEVICE
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
ADG714
ADG714
SCLK
DIN
S1A
S4A
DA
1/2 of ADG739
SYNC
S3A
S2A
FROM
 CONTROLLER
OR DSP
SYNC1
SYNC2
SYNC
SYNC
SYNC
SYNC
SCLK
DIN
V
DD
OTHER
SPI
DEVICE
R
VDD
R
VDD
R
VDD
R
VDD
Figure 8. Addressing Multiple ADG714s Using an
ADG739
C