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ADG714/ADG715

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 www.analog.com

Fax: © Analog Devices, Inc.,

CMOS, Low Voltage

Serially Controlled, Octal SPST Switches

FUNCTIONAL BLOCK DIAGRAMS

ADG714

DOUT

INPUT SHIFT

SCLK DIN SYNC RESET

ADG715

INTERFACE

LOGIC

SDA SCL A0 A1

RESET

FEATURES

ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface

ADG715 I

C™-Compatible Interface

2.7 V to 5.5 V Single Supply

2.5 V Dual Supply

2.5  On Resistance

0.6  On Resistance Flatness

100 pA Leakage Currents

Octal SPST

Power-On Reset

Fast Switching Times

TTL/CMOS-Compatible

Small TSSOP Package

APPLICATIONS

Data Acquisition Systems

Communication Systems

Relay Replacement

Audio and Video Switching

GENERAL DESCRIPTION

The ADG714/ADG715 are CMOS, octal SPST (single-pole,

single-throw) switches controlled via either a 2- or 3-wire serial

interface. On resistance is closely matched between switches and

very flat over the full signal range. Each switch conducts equally

well in both directions and the input signal range extends to the

supplies. Data is written to these devices in the form of 8 bits,

each bit corresponding to one channel.

The ADG714 uses a 3-wire serial interface that is compatible

with SPI

, QSPI,

and MICROWIRE

and most DSP interface

standards. The output of the shift register DOUT enables a

number of these parts to be daisy chained.

The ADG715 uses a 2-wire serial interface that is compatible

with the I

C interface standard. The ADG715 has four hard wired

addresses, selectable from two external address pins (A0 and A1).

This allows the 2 LSBs of the 7-bit slave address to be set by

the user. A maximum of four of these devices may be connected

to the bus.

On power-up of these devices, all switches are in the OFF con-

dition, and the internal registers contain all zeros.

Low power consumption and operating supply range of 2.7 V to

5.5 V make this part ideal for many applications. These parts

may also be supplied from a dual ± 2.5 V supply. The ADG714

and ADG715 are available in a small 24-lead TSSOP package.

PRODUCT HIGHLIGHTS

1. 2- or 3-wire serial interface

2. Single/dual supply operation. The ADG714 and ADG715

are fully speciﬁed and guaranteed with 3 V, 5 V, and ± 2.5 V

supply rails.

3. Low on resistance, typically 2.5 Ω

4. Low leakage

5. Power-on reset

6. Small 24-lead TSSOP package

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corporation.

C is a trademark of Philips Corporation.

2013

781/461-3113

Document Feedback

Summary of content (16 pages)

PAGE 1
a CMOS, Low Voltage Serially Controlled, Octal SPST Switches ADG714/ADG715 FEATURES ADG714 SPI™/QSPI™/MICROWIRE™-Compatible Interface ADG715 I2C™-Compatible Interface 2.7 V to 5.5 V Single Supply 2.5 V Dual Supply 2.5 On Resistance 0.
PAGE 2
ADG714/ADG715–SPECIFICATIONS1(V Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) B Version –40 C +25 C to +85 C 2.5 4.
PAGE 3
1 SPECIFICATIONS ADG714/ADG715 (VDD = 3 V 10%, VSS = 0 V, GND = 0 V unless otherwise noted.
PAGE 4
ADG714/ADG715–SPECIFICATIONS1 DUAL SUPPLY (V DD = +2.5 V ± 10%, VSS = −2.5 V ± 10%, GND = 0 V unless otherwise noted.) B Version –40 C +25 C to +85 C Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 2.5 4.5 On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT(ON)) 0.6 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.
PAGE 5
ADG714/ADG715 ADG714 TIMING CHARACTERISTICS1, 2 (V DD = 2.7 V to 5.5 V. All speciﬁcations –40 C to +85 C unless otherwise noted.) Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 3 30 33 13 13 0 5 4.
PAGE 6
ADG714/ADG715 ADG715 TIMING CHARACTERISTICS1 (V DD = 2.7 V to 5.5 V. All speciﬁcations –40 C to +85 C unless otherwise noted.) Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCL t1 t2 t3 t4 t5 t6 2 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.
PAGE 7
ADG714/ADG715 ABSOLUTE MAXIMUM RATINGS 1 (TA = 25°C unless otherwise noted.) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V Analog Inputs2 . . . . . . . . . . . . . . . . . VSS –0.3 V to VDD +0.3 V or 30 mA, Whichever Occurs First Digital Inputs2 . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.
PAGE 8
ADG714/ADG715 ADG714 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 SCLK 2 3 VDD DIN 4 5, 7, 9, 11, 14, 16, 18, 20 6, 8, 10, 12, 13, 15, 17, 19 21 22 GND Sx Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices can accommodate serial input rates of up to 30 MHz. Positive Analog Supply Voltage. Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input.
PAGE 9
ADG714/ADG715 TERMINOLOGY VDD VSS IDD ISS GND S D RON ΔRON Most positive power supply potential. Most negative power supply in a dual supply application. In single supply applications, this should be tied to ground. Positive Supply Current Negative Supply Current Ground (0 V) Reference Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Ohmic resistance between D and S On resistance match between any two channels, i.e., RON max–RON min.
PAGE 10
ADG714/ADG715 –Typical Performance Characteristics 8 8 TA = 25 C VSS = GND 7 6 6 VDD = 2.7V ON RESISTANCE – ON RESISTANCE – VDD = 3V VSS = GND 7 5 VDD = 3.3V 4 VDD = 4.5V VDD = 5.5V 3 +85 C 4 –40 C 3 2 2 1 1 0 +25 C 5 0 0 1 2 3 4 VD, VS, DRAIN OR SOURCE VOLTAGE – V 5 0.5 0 1.0 1.5 2.0 TPC 1. On Resistance as a Function of VD (VS) Single Supply TPC 4.
PAGE 11
ADG714/ADG715 0.04 0.1 VDD = 3V VSS = GND TA = 25 C 0.02 VDD = 3V VSS = GND VD = 3V/1V VS = 1V/3V 0.05 0 I S (OFF) I D (OFF) I D , I S (ON) CURRENT – nA CURRENT – nA I S , I D (ON) –0.02 0 I D (OFF) I S (OFF) –0.05 –0.04 0 0.5 1.0 1.5 VOLTAGE – V 2.0 –0.1 10 3.0 2.5 TPC 7. Leakage Currents as a Function of VD (VS) 20 30 50 60 40 TEMPERATURE – C 80 70 TPC 10. Leakage Currents as a Function of Temperature 0.04 0 VDD = +2.5V VSS = –2.
PAGE 12
ADG714/ADG715 GENERAL DESCRIPTION –40 VDD = 5V TA = 25 C The ADG714 and ADG715 are serially controlled, octal SPST switches, controlled by either a 2- or 3-wire interface. Each bit of the 8-bit serial word corresponds to one switch of the part. A Logic 1 in the particular bit position turns on the switch, while a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches ON.
PAGE 13
ADG714/ADG715 The 2-wire serial bus protocol operates as follows: A repeated write function gives the user flexibility to update the matrix switch a number of times after addressing the part only once. During the write cycle, each data byte will update the conﬁguration of the switches.
PAGE 14
ADG714/ADG715 APPLICATIONS Multiple Devices On One Bus Power Supply Sequencing When using CMOS devices, care must be taken to ensure correct power-supply sequencing. Incorrect power-supply sequencing can result in the device being subjected to stresses beyond those maximum ratings listed in the data sheet. Digital and analog inputs should always be applied after power supplies and ground.
PAGE 15
ADG714/ADG715 devices on the SPI bus. Figure 8 illustrates the ADG739 and multiple ADG714s in such a typical configuration. All devices receive the same serial clock and serial data, but only one device will receive the SYNC signal at any one time. The ADG739 is a serially controlled device also. One bit programmable pin of the microcontroller is used to enable the ADG739 via SYNC2, while another bit programmable pin is used as the chip select for the other serial devices, SYNC1.
PAGE 16
ADG714/ADG715 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 1.