Datasheet

ADG633
Rev. A | Page 13 of 16
EN
0.1µF0.1µF
V
S
V
OUT
50Ω
A2
A1
A0
GND
S1A
S1B
D1
V
IN
ADG633
R
L
300Ω
C
L
35pF
V
SS
V
DD
V
SS
V
DD
0.9V
OUT
50% 50%
3V
0V
V
OUT
0V
ENABLE
DRIVE (VIN)
OUTPUT
0.9V
OUT
t
OFF
(EN)
t
ON
(EN)
03275-026
Figure 26. Enable Delay, t
ON
(
EN
), t
OFF
(
EN
)
A2
A1
A0
GND
D
ADG633
S
V
OUT
V
DD
V
SS
V
DD
V
SS
V
S
V
IN
R
S
C
L
1nF
EN
3V
0V
V
OUT
LOGIC INPUT
(V
IN
)
Q
INJ
= C
L
× ΔV
OUT
ΔV
OUT
03275-027
Figure 27. Charge Injection
V
DD
V
SS
V
DD
V
SS
EN
A2
A1
A0
GND
S
D
50Ω
V
OUT
V
S
LOGIC 1
0.1µF 0.1µF
NETWORK
ANALYZER
50Ω
R
L
50Ω
OFF ISOLATION = 20 log
V
OUT
V
S
03275-028
Figure 28. Off Isolation
V
DD
V
SS
V
DD
V
SS
EN
A2
A1
A0
GND
S
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
R
L
50Ω
V
OUT
50Ω
V
S
0.1µF 0.1µF
NETWORK
ANALYZER
03275-029
Figure 29. Bandwidth
EN
A2
A1
A0
GND
SA
DA
0.1µF
V
OUT
DB
50Ω
V
S
ADG633
CROSSTALK = 20 log
V
OUT
V
S
0.1µF
R
L
50Ω
NETWORK
ANALYZER
NETWORK
ANALYZER
50Ω
V
DD
V
SS
V
DD
V
SS
03275-030
Figure 30. Channel-to-Channel Crosstalk