Datasheet

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High Voltage Latch-Up Proof,

Dual SPDT Switches

ADG5436

Rev. A

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FEATURES

Latch-up proof

8 kV HBM ESD rating

Low on resistance (<10 Ω)

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

APPLICATIONS

Relay replacement

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAMS

ADG5436

S1A

S1B

IN1

S2A

S2B

IN2

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

09204-001

Figure 1. TSSOP Package

ADG5436

S2A

S2B

S1A

S1B

IN2 ENIN1

LOGIC

09204-002

SWITCHES SHOWN FOR A LOGIC 1 INPUT.

Figure 2. LFCSP Package

GENERAL DESCRIPTION

The ADG5436 is a monolithic CMOS device containing two

independently selectable single-pole/single-throw (SPDT)

switches. An EN input on the LFCSP package enables or

disables the device. When disabled, all channels switch off. Each

switch conducts equally well in both directions when on and

has an input signal range that extends to the supplies. In the off

condition, signal levels up to the supplies are blocked. Both

switches exhibit break-before-make switching action for use in

multiplexer applications.

The on-resistance profile is very flat over the full analog input

range, ensuring excellent linearity and low distortion when

switching audio signals.

PRODUCT HIGHLIGHTS

1. Trench isolation guards against latch-up. A dielectric trench

separates the P and N channel transistors thereby preventing

latch-up even under severe overvoltage conditions.

2. Low R

3. Dual-supply operation. For applications where the analog

signal is bipolar, the ADG5436 can be operated from dual

supplies up to ±22 V.

4. Single-supply operation. For applications where the analog

signal is unipolar, the ADG5436 can be operated from a

single-rail power supply up to 40 V.

5. 3 V logic compatible digital inputs: V

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

logic power supply required.

Summary of content (20 pages)

PAGE 1
High Voltage Latch-Up Proof, Dual SPDT Switches ADG5436 FEATURES Latch-up proof 8 kV HBM ESD rating Low on resistance (<10 Ω) ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range FUNCTIONAL BLOCK DIAGRAMS ADG5436 S1A D1 S1B IN1 IN2 S2A APPLICATIONS D2 Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication sys
PAGE 2
ADG5436 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 Functional Block Diagrams .............................................................
PAGE 3
ADG5436 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 9.8 11 0.35 0.7 1.2 1.6 ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.
PAGE 4
ADG5436 Parameter POWER REQUIREMENTS IDD ISS 25°C −40°C to +85°C 45 55 0.001 −40°C to +125°C 70 1 VDD/VSS 1 ±9/±22 Unit µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2.
PAGE 5
ADG5436 Parameter Insertion Loss 25°C −0.6 CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 18 63 82 ISS −40°C to +85°C −40°C to +125°C pF typ pF typ pF typ 50 70 0.
PAGE 6
ADG5436 Parameter Off Isolation 25°C −78 −40°C to +85°C Unit dB typ Channel-to-Channel Crosstalk −58 dB typ Total Harmonic Distortion + Noise 0.075 % typ −3 dB Bandwidth Insertion Loss 106 −1.
PAGE 7
ADG5436 Parameter tOFF Break-Before-Make Time Delay, tD 25°C 127 179 55 −40°C to +85°C −40°C to +125°C Charge Injection, QINJ 250 Unit ns typ ns max ns typ ns min pC typ 193 215 Off Isolation −78 dB typ Channel-to-Channel Crosstalk −58 dB typ Total Harmonic Distortion + Noise 0.03 % typ −3 dB Bandwidth Insertion Loss 98 −0.
PAGE 8
ADG5436 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, Sx or Dx Pins Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.
PAGE 9
ADG5436 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B S1B 2 VSS 3 D2 NC 7 10 S2A NC 8 9 IN2 NC = NO CONNECT GND 4 ADG5436 TOP VIEW (Not to Scale) NC 5 11 09204-003 GND 6 PIN 1 INDICATOR D1 1 13 12 EN 11 VDD 10 S2B 9 D2 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. 09204-004 ADG5436 14 NC NC S1B 4 13 NC 14 NC 7 NC D1 3 S2A 8 NC 15 16 S1A 16 IN2 6 IN1 1 S1A 2 15 IN1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. LFCSP Pin Configuration Figure 3.
PAGE 10
ADG5436 TYPICAL PERFORMANCE CHARACTERISTICS 16 12 VDD = +10V VDD = +9V VSS = –10V VSS = –9V TA = 25°C 14 10 ON RESISTANCE (Ω) VDD = +11V VSS = –11V 12 ON RESISTANCE (Ω) TA = 25°C 10 8 = +13.5V VDD10 VSS = –13.5V 6 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V VDD = 36V VSS = 0V VDD = 32.4V VSS = 0V 8 6 VDD = 39.6V VSS = 0V 4 4 2 –10 –5 0 10 5 15 20 VS, VD (V) 0 0 5 10 15 20 25 30 35 40 45 09204-042 –15 09204-134 0 –20 15 09204-140 2 VS, VD (V) Figure 8.
PAGE 11
ADG5436 0.8 LEAKAGE CURRENT (nA) TA = +125°C 20 TA = +85°C 15 TA = +25°C TA = –40°C 10 5 ID (OFF) – + 0.4 IS (OFF) + – 0.2 0 ID, IS (ON) – – –0.2 IS (OFF) – + ID (OFF) + – –0.4 2 4 6 8 10 12 –0.6 09204-142 0 VS, VD (V) 0 0.6 TA = +85°C 8 TA = +25°C 6 TA = –40°C LEAKAGE CURRENT (nA) ON RESISTANCE (Ω) 10 4 2 15 20 25 30 35 40 VS, VD (V) 0 0 0.6 LEAKAGE CURRENT (nA) IS (OFF) + – 0.2 0 –0.2 ID, IS (ON) – – ID (OFF) + – IS (OFF) – + –0.
PAGE 12
ADG5436 0 –10 –20 –20 –30 –30 ACPSRR (dB) TA = 25°C –10 VDD = +15V VSS = –15V –60 –40 –70 –80 –80 –90 –90 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) DECOUPLING CAPACITORS –60 –70 –100 1k NO DECOUPLING CAPACITORS –50 –100 1k 1M 10M 20k Figure 20. ACPSRR vs. Frequency 0.10 TA = 25°C VDD = +15V VSS = –15V LOAD = 1kΩ TA = 25°C 0.09 –20 0.08 –30 0.07 THD + N (%) CROSSTALK (dB) –10 100k FREQUENCY (Hz) Figure 17. Off Isolation vs.
PAGE 13
ADG5436 400 350 300 VDD = 12V VSS = 0V VDD = 36V VSS = 0V 200 VDD = +20V VSS = –20V 150 VDD = +15V VSS = –15V 100 50 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 09204-035 TIME (ns) 250 Figure 23. tTRANSITION Time vs. Temperature Rev.
PAGE 14
ADG5436 TEST CIRCUITS ID (ON) IS (OFF) A A VD NC = NO CONNECT SxA/SxB Dx ID (OFF) VS A VD Figure 24. On Leakage 09204-024 Dx 09204-025 SxA/SxB NC Figure 28. Off Leakage VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS SxA/SxB V VS V p-p Dx Dx VIN RL 1kΩ GND Figure 25. On Resistance VDD Figure 29. THD + Noise VSS 0.1µF 0.1µF VDD VSS 0.1µF 0.
PAGE 15
ADG5436 VDD VSS VIN 50% 50% VIN 50% 50% VSS VDD SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF GND VIN 90% 90% VOUT tON tOFF 09204-026 0.1µF Figure 31. Switching Times 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx VOUT SxA RL 300Ω INx VOUT CL 35pF 80% tD tD 09204-027 GND VIN Figure 32. Break-Before-Make Time Delay tD 3V ENABLE DRIVE (VIN) 50% 50% VDD VSS VDD VSS INx SxA VS SxB 0V tON (EN) tOFF (EN) 0.9VOUT OUTPUT 0.
PAGE 16
ADG5436 TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN is the digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay between applying the digital control input and the output switching on. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. ∆RON ∆RON represents the difference between the RON of any two channels.
PAGE 17
ADG5436 TRENCH ISOLATION NMOS PMOS P-WELL N-WELL In the ADG5436, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. Rev. A | Page 17 of 20 TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 35.
PAGE 18
ADG5436 APPLICATIONS INFORMATION The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace and other harsh environments that are prone to latchup, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The ADG5436 high voltage switches allow single-supply operation from 9 V to 40 V and dual supply operation from ±9 V to ±22 V.
PAGE 19
ADG5436 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.