Datasheet

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High Voltage Latch-Up Proof,

Triple/Quad SPDT Switches

Data Sheet

ADG5433/ADG5434

Rev. C Document Feedback

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FEATURES

Latch-up proof

Human body model (HBM) ESD rating: 8 kV

Low on resistance (13.5 Ω)

±9 V to ±22 V dual-supply operation

9 V to 40 V single-supply operation

48 V supply maximum ratings

Fully specified at ±15 V, ±20 V, +12 V, and +36 V

to V

analog signal range

APPLICATIONS

Relay replacement

Automatic test equipment

Data acquisition

Instrumentation

Avionics

Audio and video switching

Communication systems

FUNCTIONAL BLOCK DIAGRAMS

Figure 1. ADG5433 TSSOP and LFCSP_WQ

Figure 2. ADG5434 TSSOP and LFCSP_WQ

GENERAL DESCRIPTION

The ADG5433 and ADG5434 are monolithic industrial CMOS

analog switches comprising three independently selectable

single-pole, double-throw (SPDT) switches and four indepen-

dently selectable SPDT switches, respectively.

All channels exhibit break-before-make switching action that

prevents momentary shorting when switching channels. An

input on the ADG5433 (LFCSP and TSSOP packages) is used to

enable or disable the device. When disabled, all channels are

switched off.

The ultralow on resistance and on-resistance flatness of these

switches make them ideal solutions for data acquisition and gain

switching applications, where low distortion is critical.

PRODUCT HIGHLIGHTS

1. Trench isolation guards against latch-up. A dielectric trench

separates the P and N channel transistors thereby preventing

latch-up even under severe overvoltage conditions.

2. Low R

3. Dual-supply operation. For applications where the analog

signal is bipolar, the ADG5433/ADG5434 can be operated

from dual supplies up to ±22 V.

4. Single-supply operation. For applications where the analog

signal is unipolar, the ADG5433/ADG5434 can be operated

from a single-rail power supply up to 40 V.

5. 3 V logic compatible digital inputs: V

INH

= 2.0 V, V

INL

= 0.8 V.

6. No V

logic power supply required.

IN1 IN2 IN3 EN

S1A

S1B

S2B

S2A

S3B

S3A

LOGIC

ADG5433

SWITCHES SHOWN FOR

A LOGIC 1 INPUT.

09207-001

IN1 IN2 IN3 IN4

S1B

S2A

S4A

S4B

S3B

LOGIC

ADG

5434

ITCHES

SHO

LOGI

C 1 INPUT.

09207-002

Summary of content (24 pages)

PAGE 1
High Voltage Latch-Up Proof, Triple/Quad SPDT Switches ADG5433/ADG5434 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof Human body model (HBM) ESD rating: 8 kV Low on resistance (13.
PAGE 2
ADG5433/ADG5434 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Continuous Current per Channel, Sx or Dx ..............................8 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................9 Functional Block Diagrams .............................................................
PAGE 3
Data Sheet ADG5433/ADG5434 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 13.5 15 0.3 0.8 1.8 2.2 ±0.05 ±0.25 ±0.1 ±0.4 ±0.1 ±0.
PAGE 4
ADG5433/ADG5434 Parameter POWER REQUIREMENTS IDD ISS Data Sheet 25°C −40°C to +85°C 45 55 0.001 70 1 ±9/±22 VDD/VSS 1 −40°C to +125°C Unit µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2.
PAGE 5
Data Sheet ADG5433/ADG5434 Parameter Insertion Loss 25°C −0.8 CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 15 23 52 ISS −40°C to +85°C Unit dB typ pF typ pF typ pF typ 50 70 0.
PAGE 6
ADG5433/ADG5434 Parameter Channel-to-Channel Crosstalk Data Sheet 25°C −60 −40°C to +85°C Unit dB typ Total Harmonic Distortion + Noise 0.1 % typ −3 dB Bandwidth 150 MHz typ Insertion Loss −0.
PAGE 7
Data Sheet Parameter Charge Injection, QINJ ADG5433/ADG5434 25°C 150 −40°C to +85°C −40°C to +125°C Unit pC typ Off Isolation −60 dB typ Channel-to-Channel Crosstalk −60 dB typ Total Harmonic Distortion + Noise 0.4 % typ −3 dB Bandwidth Insertion Loss 135 −1 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 18 28 46 pF typ pF typ pF typ VDD 1 80 100 130 9/40 Guaranteed by design; not subject to production test. Rev.
PAGE 8
ADG5433/ADG5434 Data Sheet CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Table 5. ADG5433 Parameter CONTINUOUS CURRENT, Sx OR Dx VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.
PAGE 9
Data Sheet ADG5433/ADG5434 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, Sx or Dx Pins ADG5433 ADG5434 Continuous Current, Sx or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 20-Lead TSSOP (4-Layer Board) 16-Lead LFCSP (4-Layer Board) Reflow Soldering Peak Temperature, Pb Free Rating 48 V −0.3 V to +48 V +0.
PAGE 10
ADG5433/ADG5434 Data Sheet 14 GND 13 IN1 16 S1A 15 VDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 16 GND S1A 2 15 IN1 D1 1 D1 3 14 EN S1B 2 ADG5433 11 VSS VSS S2B 3 TOP VIEW (Not to Scale) 10 S3B D3 10 S3A IN2 8 9 IN3 NOTES 1. EXPOSED PAD IS TIED TO SUBSTRATE, VSS. Figure 3. ADG5433 TSSOP Pin Configuration 09207-005 D2 S2A 7 9 D3 IN3 7 S3B 11 D2 4 S3A 8 12 6 13 IN2 6 TOP VIEW (Not to Scale) S2A 5 S2B 5 09207-003 S1B 4 ADG5433 12 EN Figure 4.
PAGE 11
ADG5433/ADG5434 20 19 18 17 16 S1A IN1 EN IN4 S4A Data Sheet IN1 1 20 IN4 18 D4 S1B 4 17 S4B VSS 5 ADG5434 16 VDD GND 6 TOP VIEW (Not to Scale) 15 NC S2B 7 14 S3B D2 8 13 D3 S2A 9 12 S3A IN2 10 11 IN3 NC = NO CONNECT ADG5434 TOP VIEW (Not to Scale) 15 14 13 12 11 D4 S4B VDD S3B D3 NOTES 1. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
PAGE 12
ADG5433/ADG5434 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 25 16 TA = 25°C TA = 25°C VDD = +10V VSS = –10V VDD = +9V VSS = –9V 14 12 VDD = +11V VSS = –11V ON RESISTANCE (Ω) ON RESISTANCE (Ω) 20 15 10 VDD = +13.5V VSS = –13.5V VDD = +15V VSS = –15V VDD = +16.5V VSS = –16.5V 10 VDD = 32.4V VSS = 0V 8 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 6 4 5 –14 –6 –10 2 –2 6 10 14 18 VS, VD (V) 0 09207-047 0 –18 0 5 10 15 25 20 30 35 40 45 VS, VD (V) Figure 7.
PAGE 13
Data Sheet ADG5433/ADG5434 40 0.4 VDD = +20V VSS = –20V VBIAS = +15V/–15V 35 ID, IS (ON) + + IS (OFF) + – 0.2 ON RESISTANCE (Ω) LEAKAGE CURRENT (nA) TA = +125°C 30 TA = +85°C 25 20 TA = +25°C 15 TA = –40°C 10 ID (OFF) – + 0 ID, IS (ON) – – –0.2 IS (OFF) – + –0.4 ID (OFF) + – 5 4 2 6 8 10 12 VS, VD (V) –0.6 50 75 100 125 Figure 16. Leakage Currents as a Function of Temperature, ±20 V Dual Supply 0.4 VDD = 36V VSS = 0V VDD = 12V VSS = 0V VBIAS = 1V/10V 0.
PAGE 14
ADG5433/ADG5434 –20 –30 –30 ACPSRR (dB) –20 –40 –50 –60 –50 –60 DECOUPLING CAPACITORS –70 –80 –80 –90 –90 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) NO DECOUPLING CAPACITORS –40 –70 –100 1k TA = 25°C VDD = +15V VSS = –15V –10 –100 1k 09207-036 OFF ISOLATION (dB) –10 0 TA = 25°C VDD = +15V VSS = –15V 100k 1M 10M FREQUENCY (Hz) Figure 19. Off Isolation vs. Frequency Figure 22. ACPSRR vs. Frequency 0 TA = 25°C –10 VDD = +15V VSS = –15V 0.12 VDD= 12V, VSS= 0V, VS = 6V p-p 0.
PAGE 15
Data Sheet ADG5433/ADG5434 350 300 VDD = +12V, VSS = 0V VDD = +36V, VSS = 0V 200 150 VDD = +15V, VSS = –15V 100 VDD = +20V, VSS = –20V 50 0 –40 –20 0 20 40 60 80 100 TEMPERATURE (°C) 120 09207-034 TIME (ns) 250 Figure 25. tTRANSITION Times vs. Temperature Rev.
PAGE 16
ADG5433/ADG5434 Data Sheet TEST CIRCUITS S1 NC D VSS 0.1µF 0.1µF A S2 A VDD ID (ON) IS (OFF) VDD 09206-023 VD VS SxA IN NETWORK ANALYZER VSS NC SxB 50Ω 50Ω VS Figure 26. On and Off Leakage Dx VIN RL 50Ω GND VOUT S OFF ISOLATION = 20 log D VOUT VS Figure 29. Off Isolation IDS 09207-021 RON = V/IDS VS VDD VSS 0.1µF 0.1µF Figure 27.
PAGE 17
Data Sheet ADG5433/ADG5434 VDD 0.1µF VSS VDD VIN 50% 50% VIN 50% 50% VSS SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF 90% 90% VOUT tON tOFF 09207-024 GND VIN Figure 32. Switching Timing 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx SxA VOUT RL 300Ω INx VOUT 80% CL 35pF tD GND tD 09207-025 VIN Figure 33. Break-Before-Make Delay, tD VDD VSS VDD VSS 0.
PAGE 18
ADG5433/ADG5434 Data Sheet TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN represents digital input capacitance. ISS ISS represents the negative supply current. tON (EN) tON (EN) represents the delay time between the 50% and 90% points of the digital input and switch on condition. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively.
PAGE 19
Data Sheet ADG5433/ADG5434 TRENCH ISOLATION In the ADG5433/ADG5434, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. PMOS P-WELL N-WELL TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 36. Trench Isolation Rev.
PAGE 20
ADG5433/ADG5434 Data Sheet APPLICATIONS INFORMATION The ADG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5433/ADG5434 high voltage switches allow single-supply operation from 9 V to 40 V and dual supply operation from ±9 V to ±22 V.
PAGE 21
Data Sheet ADG5433/ADG5434 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.
PAGE 22
ADG5433/ADG5434 Data Sheet 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.30 0.25 0.18 0.50 BSC PIN 1 INDICATOR 20 16 15 1 EXPOSED PAD 2.75 2.60 SQ 2.35 11 TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 5 10 0.25 MIN BOTTOM VIEW 0.05 MAX 0.
PAGE 23
Data Sheet ADG5433/ADG5434 NOTES Rev.